97 				harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING);  in vcn_v3_0_early_init()
176 		adev->vcn.inst[i].external.scratch9 = SOC15_REG_OFFSET(VCN, i, mmUVD_SCRATCH9);  in vcn_v3_0_sw_init()
178 		adev->vcn.inst[i].external.data0 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA0);  in vcn_v3_0_sw_init()
180 		adev->vcn.inst[i].external.data1 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA1);  in vcn_v3_0_sw_init()
182 		adev->vcn.inst[i].external.cmd = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_CMD);  in vcn_v3_0_sw_init()
184 		adev->vcn.inst[i].external.nop = SOC15_REG_OFFSET(VCN, i, mmUVD_NO_OP);  in vcn_v3_0_sw_init()
360 					 RREG32_SOC15(VCN, i, mmUVD_STATUS))) {  in vcn_v3_0_hw_fini()
432 		WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,  in vcn_v3_0_mc_resume()
434 		WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,  in vcn_v3_0_mc_resume()
436 		WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 0);  in vcn_v3_0_mc_resume()
439 		WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,  in vcn_v3_0_mc_resume()
441 		WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,  in vcn_v3_0_mc_resume()
444 		WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0,  in vcn_v3_0_mc_resume()
447 	WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE0, size);  in vcn_v3_0_mc_resume()
450 	WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,  in vcn_v3_0_mc_resume()
452 	WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,  in vcn_v3_0_mc_resume()
454 	WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET1, 0);  in vcn_v3_0_mc_resume()
455 	WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);  in vcn_v3_0_mc_resume()
458 	WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,  in vcn_v3_0_mc_resume()
460 	WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,  in vcn_v3_0_mc_resume()
462 	WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET2, 0);  in vcn_v3_0_mc_resume()
463 	WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);  in vcn_v3_0_mc_resume()
475 				VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),  in vcn_v3_0_mc_resume_dpg_mode()
478 				VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),  in vcn_v3_0_mc_resume_dpg_mode()
481 				VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
484 				VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
486 				VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
488 				VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
493 			VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),  in vcn_v3_0_mc_resume_dpg_mode()
496 			VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),  in vcn_v3_0_mc_resume_dpg_mode()
500 			VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0),  in vcn_v3_0_mc_resume_dpg_mode()
506 			VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
509 			VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
514 			VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),  in vcn_v3_0_mc_resume_dpg_mode()
517 			VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),  in vcn_v3_0_mc_resume_dpg_mode()
520 			VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
523 			VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
525 			VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
527 			VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
530 			VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
534 			VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),  in vcn_v3_0_mc_resume_dpg_mode()
537 			VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),  in vcn_v3_0_mc_resume_dpg_mode()
540 			VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
542 			VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
546 			VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
548 			VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
550 			VCN, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
552 			VCN, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
575 		WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data);  in vcn_v3_0_disable_static_power_gating()
576 		SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS,  in vcn_v3_0_disable_static_power_gating()
593 		WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data);  in vcn_v3_0_disable_static_power_gating()
594 		SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 0,  0x3F3FFFFF);  in vcn_v3_0_disable_static_power_gating()
597 	data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);  in vcn_v3_0_disable_static_power_gating()
603 	WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data);  in vcn_v3_0_disable_static_power_gating()
612 		data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);  in vcn_v3_0_enable_static_power_gating()
615 		WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data);  in vcn_v3_0_enable_static_power_gating()
631 		WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data);  in vcn_v3_0_enable_static_power_gating()
647 		SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, data, 0x3F3FFFFF);  in vcn_v3_0_enable_static_power_gating()
664 	data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);  in vcn_v3_0_disable_clock_gating()
671 	WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);  in vcn_v3_0_disable_clock_gating()
673 	data = RREG32_SOC15(VCN, inst, mmUVD_CGC_GATE);  in vcn_v3_0_disable_clock_gating()
695 	WREG32_SOC15(VCN, inst, mmUVD_CGC_GATE, data);  in vcn_v3_0_disable_clock_gating()
697 	SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_CGC_GATE, 0,  0xFFFFFFFF);  in vcn_v3_0_disable_clock_gating()
699 	data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);  in vcn_v3_0_disable_clock_gating()
720 	WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);  in vcn_v3_0_disable_clock_gating()
722 	data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE);  in vcn_v3_0_disable_clock_gating()
754 	WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE, data);  in vcn_v3_0_disable_clock_gating()
756 	data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2);  in vcn_v3_0_disable_clock_gating()
762 	WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2, data);  in vcn_v3_0_disable_clock_gating()
764 	data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL);  in vcn_v3_0_disable_clock_gating()
784 	WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data);  in vcn_v3_0_disable_clock_gating()
820 		VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);  in vcn_v3_0_clock_gating_dpg_mode()
824 		VCN, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect);  in vcn_v3_0_clock_gating_dpg_mode()
828 		VCN, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);  in vcn_v3_0_clock_gating_dpg_mode()
832 		VCN, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);  in vcn_v3_0_clock_gating_dpg_mode()
848 	data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);  in vcn_v3_0_enable_clock_gating()
855 	WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);  in vcn_v3_0_enable_clock_gating()
857 	data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);  in vcn_v3_0_enable_clock_gating()
878 	WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);  in vcn_v3_0_enable_clock_gating()
880 	data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL);  in vcn_v3_0_enable_clock_gating()
900 	WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data);  in vcn_v3_0_enable_clock_gating()
909 	WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1,  in vcn_v3_0_start_dpg_mode()
912 	tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS);  in vcn_v3_0_start_dpg_mode()
915 	WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp);  in vcn_v3_0_start_dpg_mode()
928 		VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);  in vcn_v3_0_start_dpg_mode()
932 		VCN, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect);  in vcn_v3_0_start_dpg_mode()
944 		VCN, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect);  in vcn_v3_0_start_dpg_mode()
947 		VCN, inst_idx, mmUVD_MPC_CNTL),  in vcn_v3_0_start_dpg_mode()
951 		VCN, inst_idx, mmUVD_MPC_SET_MUXA0),  in vcn_v3_0_start_dpg_mode()
958 		VCN, inst_idx, mmUVD_MPC_SET_MUXB0),  in vcn_v3_0_start_dpg_mode()
965 		VCN, inst_idx, mmUVD_MPC_SET_MUX),  in vcn_v3_0_start_dpg_mode()
973 		VCN, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect);  in vcn_v3_0_start_dpg_mode()
975 		VCN, inst_idx, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);  in vcn_v3_0_start_dpg_mode()
979 		VCN, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect);  in vcn_v3_0_start_dpg_mode()
983 		VCN, inst_idx, mmUVD_RB_ARB_CTRL), 0, 0, indirect);  in vcn_v3_0_start_dpg_mode()
988 		VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);  in vcn_v3_0_start_dpg_mode()
992 		VCN, inst_idx, mmUVD_MASTINT_EN),  in vcn_v3_0_start_dpg_mode()
997 		VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);  in vcn_v3_0_start_dpg_mode()
1012 	WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp);  in vcn_v3_0_start_dpg_mode()
1015 	WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),  in vcn_v3_0_start_dpg_mode()
1020 	WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0);  in vcn_v3_0_start_dpg_mode()
1023 	WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR,  in vcn_v3_0_start_dpg_mode()
1027 	WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,  in vcn_v3_0_start_dpg_mode()
1029 	WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,  in vcn_v3_0_start_dpg_mode()
1033 	WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0);  in vcn_v3_0_start_dpg_mode()
1035 	WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0);  in vcn_v3_0_start_dpg_mode()
1037 	ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR);  in vcn_v3_0_start_dpg_mode()
1038 	WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR,  in vcn_v3_0_start_dpg_mode()
1042 	WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),  in vcn_v3_0_start_dpg_mode()
1070 		tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;  in vcn_v3_0_start()
1071 		WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp);  in vcn_v3_0_start()
1077 		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),  in vcn_v3_0_start()
1081 		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0,  in vcn_v3_0_start()
1085 		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0,  in vcn_v3_0_start()
1088 		tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);  in vcn_v3_0_start()
1091 		WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);  in vcn_v3_0_start()
1094 		tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL);  in vcn_v3_0_start()
1095 		WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp |  in vcn_v3_0_start()
1102 		tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL);  in vcn_v3_0_start()
1105 		WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp);  in vcn_v3_0_start()
1108 		WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0,  in vcn_v3_0_start()
1115 		WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0,  in vcn_v3_0_start()
1122 		WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX,  in vcn_v3_0_start()
1130 		WREG32_SOC15(VCN, i, mmUVD_GFX10_ADDR_CONFIG,  in vcn_v3_0_start()
1134 		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0,  in vcn_v3_0_start()
1138 		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,  in vcn_v3_0_start()
1145 				status = RREG32_SOC15(VCN, i, mmUVD_STATUS);  in vcn_v3_0_start()
1155 			WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),  in vcn_v3_0_start()
1159 			WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,  in vcn_v3_0_start()
1172 		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN),  in vcn_v3_0_start()
1177 		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0,  in vcn_v3_0_start()
1180 		WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0);  in vcn_v3_0_start()
1190 		WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp);  in vcn_v3_0_start()
1193 		WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,  in vcn_v3_0_start()
1195 		WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,  in vcn_v3_0_start()
1199 		WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0);  in vcn_v3_0_start()
1201 		ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR);  in vcn_v3_0_start()
1202 		WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR,  in vcn_v3_0_start()
1205 		WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));  in vcn_v3_0_start()
1206 		WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));  in vcn_v3_0_start()
1207 		WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr);  in vcn_v3_0_start()
1208 		WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));  in vcn_v3_0_start()
1209 		WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4);  in vcn_v3_0_start()
1212 		WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));  in vcn_v3_0_start()
1213 		WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));  in vcn_v3_0_start()
1214 		WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr);  in vcn_v3_0_start()
1215 		WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));  in vcn_v3_0_start()
1216 		WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4);  in vcn_v3_0_start()
1273 		MMSCH_V3_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1281 			MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1284 			MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1288 			MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1292 			MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1295 			MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1299 			MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1304 		MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1309 		MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1312 		MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1315 		MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1318 		MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1324 		MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1327 		MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1330 		MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1333 		MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1341 			MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1344 			MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1347 			MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1355 		MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1358 		MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1368 		MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v3_0_start_sriov()
1392 	WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr));  in vcn_v3_0_start_sriov()
1393 	WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr));  in vcn_v3_0_start_sriov()
1396 	tmp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID);  in vcn_v3_0_start_sriov()
1400 	WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, tmp);  in vcn_v3_0_start_sriov()
1404 	WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size);  in vcn_v3_0_start_sriov()
1407 	WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0);  in vcn_v3_0_start_sriov()
1413 	WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, param);  in vcn_v3_0_start_sriov()
1419 		resp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP);  in vcn_v3_0_start_sriov()
1442 	SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,  in vcn_v3_0_stop_dpg_mode()
1446 	tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR);  in vcn_v3_0_stop_dpg_mode()
1447 	SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);  in vcn_v3_0_stop_dpg_mode()
1449 	tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2);  in vcn_v3_0_stop_dpg_mode()
1450 	SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF);  in vcn_v3_0_stop_dpg_mode()
1452 	tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;  in vcn_v3_0_stop_dpg_mode()
1453 	SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);  in vcn_v3_0_stop_dpg_mode()
1455 	SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,  in vcn_v3_0_stop_dpg_mode()
1459 	WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0,  in vcn_v3_0_stop_dpg_mode()
1480 		r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);  in vcn_v3_0_stop()
1488 		r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);  in vcn_v3_0_stop()
1493 		tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2);  in vcn_v3_0_stop()
1495 		WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp);  in vcn_v3_0_stop()
1498 		r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);  in vcn_v3_0_stop()
1503 		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL),  in vcn_v3_0_stop()
1508 		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),  in vcn_v3_0_stop()
1513 		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,  in vcn_v3_0_stop()
1517 		tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);  in vcn_v3_0_stop()
1519 		WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);  in vcn_v3_0_stop()
1520 		tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);  in vcn_v3_0_stop()
1522 		WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);  in vcn_v3_0_stop()
1525 		WREG32_SOC15(VCN, i, mmUVD_STATUS, 0);  in vcn_v3_0_stop()
1551 		reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) &  in vcn_v3_0_pause_dpg_mode()
1555 			ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1,  in vcn_v3_0_pause_dpg_mode()
1561 				WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data);  in vcn_v3_0_pause_dpg_mode()
1564 				SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE,  in vcn_v3_0_pause_dpg_mode()
1569 				WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),  in vcn_v3_0_pause_dpg_mode()
1576 				WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr);  in vcn_v3_0_pause_dpg_mode()
1577 				WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));  in vcn_v3_0_pause_dpg_mode()
1578 				WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4);  in vcn_v3_0_pause_dpg_mode()
1579 				WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));  in vcn_v3_0_pause_dpg_mode()
1580 				WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));  in vcn_v3_0_pause_dpg_mode()
1584 				WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr);  in vcn_v3_0_pause_dpg_mode()
1585 				WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));  in vcn_v3_0_pause_dpg_mode()
1586 				WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4);  in vcn_v3_0_pause_dpg_mode()
1587 				WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));  in vcn_v3_0_pause_dpg_mode()
1588 				WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));  in vcn_v3_0_pause_dpg_mode()
1591 				WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),  in vcn_v3_0_pause_dpg_mode()
1594 				SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS,  in vcn_v3_0_pause_dpg_mode()
1600 			WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data);  in vcn_v3_0_pause_dpg_mode()
1619 	return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR);  in vcn_v3_0_dec_ring_get_rptr()
1636 		return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR);  in vcn_v3_0_dec_ring_get_wptr()
1654 		WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));  in vcn_v3_0_dec_ring_set_wptr()
1700 		return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR);  in vcn_v3_0_enc_ring_get_rptr()
1702 		return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2);  in vcn_v3_0_enc_ring_get_rptr()
1720 			return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR);  in vcn_v3_0_enc_ring_get_wptr()
1725 			return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2);  in vcn_v3_0_enc_ring_get_wptr()
1745 			WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));  in vcn_v3_0_enc_ring_set_wptr()
1752 			WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));  in vcn_v3_0_enc_ring_set_wptr()
1826 		ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE);  in vcn_v3_0_is_idle()
1841 		ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE,  in vcn_v3_0_wait_for_idle()
1862 			if (RREG32_SOC15(VCN, i, mmUVD_STATUS) != UVD_STATUS__IDLE)  in vcn_v3_0_set_clockgating_state()