Lines Matching refs:VCN
87 harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING); in vcn_v2_5_early_init()
175 adev->vcn.inst[j].external.scratch9 = SOC15_REG_OFFSET(VCN, j, mmUVD_SCRATCH9); in vcn_v2_5_sw_init()
177 adev->vcn.inst[j].external.data0 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA0); in vcn_v2_5_sw_init()
179 adev->vcn.inst[j].external.data1 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA1); in vcn_v2_5_sw_init()
181 adev->vcn.inst[j].external.cmd = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_CMD); in vcn_v2_5_sw_init()
183 adev->vcn.inst[j].external.nop = SOC15_REG_OFFSET(VCN, j, mmUVD_NO_OP); in vcn_v2_5_sw_init()
330 RREG32_SOC15(VCN, i, mmUVD_STATUS))) in vcn_v2_5_hw_fini()
397 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v2_5_mc_resume()
399 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v2_5_mc_resume()
401 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0, 0); in vcn_v2_5_mc_resume()
404 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v2_5_mc_resume()
406 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v2_5_mc_resume()
409 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0, in vcn_v2_5_mc_resume()
412 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE0, size); in vcn_v2_5_mc_resume()
415 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, in vcn_v2_5_mc_resume()
417 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, in vcn_v2_5_mc_resume()
419 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET1, 0); in vcn_v2_5_mc_resume()
420 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); in vcn_v2_5_mc_resume()
423 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, in vcn_v2_5_mc_resume()
425 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, in vcn_v2_5_mc_resume()
427 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET2, 0); in vcn_v2_5_mc_resume()
428 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); in vcn_v2_5_mc_resume()
431 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, in vcn_v2_5_mc_resume()
433 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, in vcn_v2_5_mc_resume()
435 WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_OFFSET0, 0); in vcn_v2_5_mc_resume()
436 WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_SIZE0, in vcn_v2_5_mc_resume()
450 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v2_5_mc_resume_dpg_mode()
453 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v2_5_mc_resume_dpg_mode()
456 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
459 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
461 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
463 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
468 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v2_5_mc_resume_dpg_mode()
471 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v2_5_mc_resume_dpg_mode()
475 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), in vcn_v2_5_mc_resume_dpg_mode()
481 VCN, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
484 VCN, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
489 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), in vcn_v2_5_mc_resume_dpg_mode()
492 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), in vcn_v2_5_mc_resume_dpg_mode()
495 VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
498 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
500 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
502 VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
505 VCN, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
509 VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), in vcn_v2_5_mc_resume_dpg_mode()
512 VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), in vcn_v2_5_mc_resume_dpg_mode()
515 VCN, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
517 VCN, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
521 VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), in vcn_v2_5_mc_resume_dpg_mode()
524 VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), in vcn_v2_5_mc_resume_dpg_mode()
527 VCN, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
529 VCN, 0, mmUVD_VCPU_NONCACHE_SIZE0), in vcn_v2_5_mc_resume_dpg_mode()
534 VCN, 0, mmUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
553 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_disable_clock_gating()
560 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_disable_clock_gating()
562 data = RREG32_SOC15(VCN, i, mmUVD_CGC_GATE); in vcn_v2_5_disable_clock_gating()
584 WREG32_SOC15(VCN, i, mmUVD_CGC_GATE, data); in vcn_v2_5_disable_clock_gating()
586 SOC15_WAIT_ON_RREG(VCN, i, mmUVD_CGC_GATE, 0, 0xFFFFFFFF); in vcn_v2_5_disable_clock_gating()
588 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_disable_clock_gating()
609 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_disable_clock_gating()
612 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE); in vcn_v2_5_disable_clock_gating()
637 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE, data); in vcn_v2_5_disable_clock_gating()
639 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL); in vcn_v2_5_disable_clock_gating()
650 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data); in vcn_v2_5_disable_clock_gating()
687 VCN, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
691 VCN, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
695 VCN, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
699 VCN, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
718 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_enable_clock_gating()
725 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_enable_clock_gating()
727 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_enable_clock_gating()
747 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_enable_clock_gating()
749 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL); in vcn_v2_5_enable_clock_gating()
760 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data); in vcn_v2_5_enable_clock_gating()
771 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1, in vcn_v2_5_start_dpg_mode()
774 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS); in vcn_v2_5_start_dpg_mode()
777 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp); in vcn_v2_5_start_dpg_mode()
790 VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v2_5_start_dpg_mode()
794 VCN, 0, mmUVD_MASTINT_EN), 0, 0, indirect); in vcn_v2_5_start_dpg_mode()
806 VCN, 0, mmUVD_LMI_CTRL), tmp, 0, indirect); in vcn_v2_5_start_dpg_mode()
809 VCN, 0, mmUVD_MPC_CNTL), in vcn_v2_5_start_dpg_mode()
813 VCN, 0, mmUVD_MPC_SET_MUXA0), in vcn_v2_5_start_dpg_mode()
820 VCN, 0, mmUVD_MPC_SET_MUXB0), in vcn_v2_5_start_dpg_mode()
827 VCN, 0, mmUVD_MPC_SET_MUX), in vcn_v2_5_start_dpg_mode()
835 VCN, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect); in vcn_v2_5_start_dpg_mode()
837 VCN, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect); in vcn_v2_5_start_dpg_mode()
841 VCN, 0, mmUVD_LMI_CTRL2), 0, 0, indirect); in vcn_v2_5_start_dpg_mode()
845 VCN, 0, mmUVD_RB_ARB_CTRL), 0, 0, indirect); in vcn_v2_5_start_dpg_mode()
850 VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v2_5_start_dpg_mode()
854 VCN, 0, mmUVD_MASTINT_EN), in vcn_v2_5_start_dpg_mode()
870 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp); in vcn_v2_5_start_dpg_mode()
873 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), in vcn_v2_5_start_dpg_mode()
879 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0); in vcn_v2_5_start_dpg_mode()
882 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR, in vcn_v2_5_start_dpg_mode()
886 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, in vcn_v2_5_start_dpg_mode()
888 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, in vcn_v2_5_start_dpg_mode()
892 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0); in vcn_v2_5_start_dpg_mode()
894 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0); in vcn_v2_5_start_dpg_mode()
896 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR); in vcn_v2_5_start_dpg_mode()
897 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, in vcn_v2_5_start_dpg_mode()
902 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), in vcn_v2_5_start_dpg_mode()
926 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), 0, in vcn_v2_5_start()
930 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; in vcn_v2_5_start()
931 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp); in vcn_v2_5_start()
944 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), in vcn_v2_5_start()
948 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0, in vcn_v2_5_start()
952 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL); in vcn_v2_5_start()
954 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | 0x8| in vcn_v2_5_start()
961 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL); in vcn_v2_5_start()
964 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp); in vcn_v2_5_start()
967 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0, in vcn_v2_5_start()
974 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0, in vcn_v2_5_start()
981 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX, in vcn_v2_5_start()
994 WREG32_SOC15(VCN, i, mmUVD_GFX8_ADDR_CONFIG, in vcn_v2_5_start()
996 WREG32_SOC15(VCN, i, mmUVD_GFX8_ADDR_CONFIG, in vcn_v2_5_start()
1000 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0, in vcn_v2_5_start()
1004 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0, in vcn_v2_5_start()
1007 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, in vcn_v2_5_start()
1014 status = RREG32_SOC15(VCN, i, mmUVD_STATUS); in vcn_v2_5_start()
1027 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), in vcn_v2_5_start()
1031 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, in vcn_v2_5_start()
1044 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), in vcn_v2_5_start()
1049 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0, in vcn_v2_5_start()
1052 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0); in vcn_v2_5_start()
1062 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp); in vcn_v2_5_start()
1066 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, in vcn_v2_5_start()
1068 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, in vcn_v2_5_start()
1072 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0); in vcn_v2_5_start()
1074 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR); in vcn_v2_5_start()
1075 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR, in vcn_v2_5_start()
1081 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v2_5_start()
1082 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_5_start()
1083 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v2_5_start()
1084 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v2_5_start()
1085 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4); in vcn_v2_5_start()
1090 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in vcn_v2_5_start()
1091 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v2_5_start()
1092 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v2_5_start()
1093 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v2_5_start()
1094 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4); in vcn_v2_5_start()
1115 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr)); in vcn_v2_5_mmsch_start()
1116 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr)); in vcn_v2_5_mmsch_start()
1119 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID); in vcn_v2_5_mmsch_start()
1123 WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, data); in vcn_v2_5_mmsch_start()
1126 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size); in vcn_v2_5_mmsch_start()
1129 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0); in vcn_v2_5_mmsch_start()
1135 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, 0x10000001); in vcn_v2_5_mmsch_start()
1137 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); in vcn_v2_5_mmsch_start()
1141 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); in vcn_v2_5_mmsch_start()
1184 SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), in vcn_v2_5_sriov_start()
1191 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1195 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1200 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0), 0); in vcn_v2_5_sriov_start()
1203 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1207 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1212 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0), in vcn_v2_5_sriov_start()
1217 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE0), in vcn_v2_5_sriov_start()
1220 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1224 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1228 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET1), in vcn_v2_5_sriov_start()
1231 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE1), in vcn_v2_5_sriov_start()
1234 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1239 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1244 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET2), in vcn_v2_5_sriov_start()
1247 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE2), in vcn_v2_5_sriov_start()
1254 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_BASE_LO), in vcn_v2_5_sriov_start()
1257 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_BASE_HI), in vcn_v2_5_sriov_start()
1260 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_SIZE), in vcn_v2_5_sriov_start()
1266 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1270 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1282 SOC15_REG_OFFSET(VCN, i, mmUVD_RBC_RB_CNTL), tmp); in vcn_v2_5_sriov_start()
1302 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v2_5_stop_dpg_mode()
1306 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR); in vcn_v2_5_stop_dpg_mode()
1307 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v2_5_stop_dpg_mode()
1309 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2); in vcn_v2_5_stop_dpg_mode()
1310 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); in vcn_v2_5_stop_dpg_mode()
1312 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; in vcn_v2_5_stop_dpg_mode()
1313 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v2_5_stop_dpg_mode()
1315 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v2_5_stop_dpg_mode()
1319 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0, in vcn_v2_5_stop_dpg_mode()
1339 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v2_5_stop()
1347 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); in vcn_v2_5_stop()
1352 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2); in vcn_v2_5_stop()
1354 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp); in vcn_v2_5_stop()
1358 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); in vcn_v2_5_stop()
1363 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), in vcn_v2_5_stop()
1368 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), in vcn_v2_5_stop()
1373 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, in vcn_v2_5_stop()
1377 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0); in vcn_v2_5_stop()
1382 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), in vcn_v2_5_stop()
1404 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) & in vcn_v2_5_pause_dpg_mode()
1408 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1, in vcn_v2_5_pause_dpg_mode()
1416 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); in vcn_v2_5_pause_dpg_mode()
1419 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE, in vcn_v2_5_pause_dpg_mode()
1424 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), in vcn_v2_5_pause_dpg_mode()
1432 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v2_5_pause_dpg_mode()
1433 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v2_5_pause_dpg_mode()
1434 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4); in vcn_v2_5_pause_dpg_mode()
1435 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v2_5_pause_dpg_mode()
1436 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_5_pause_dpg_mode()
1442 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v2_5_pause_dpg_mode()
1443 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v2_5_pause_dpg_mode()
1444 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4); in vcn_v2_5_pause_dpg_mode()
1445 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in vcn_v2_5_pause_dpg_mode()
1446 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v2_5_pause_dpg_mode()
1450 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), in vcn_v2_5_pause_dpg_mode()
1453 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, in vcn_v2_5_pause_dpg_mode()
1458 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); in vcn_v2_5_pause_dpg_mode()
1459 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1, in vcn_v2_5_pause_dpg_mode()
1479 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR); in vcn_v2_5_dec_ring_get_rptr()
1496 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR); in vcn_v2_5_dec_ring_get_wptr()
1514 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_5_dec_ring_set_wptr()
1560 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR); in vcn_v2_5_enc_ring_get_rptr()
1562 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2); in vcn_v2_5_enc_ring_get_rptr()
1580 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR); in vcn_v2_5_enc_ring_get_wptr()
1585 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2); in vcn_v2_5_enc_ring_get_wptr()
1605 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_5_enc_ring_set_wptr()
1612 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v2_5_enc_ring_set_wptr()
1683 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v2_5_is_idle()
1697 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v2_5_wait_for_idle()