90 	WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));  in uvd_v4_2_ring_set_wptr()
266 	WREG32(mmUVD_CGC_GATE, 0);  in uvd_v4_2_start()
273 	WREG32(mmUVD_VCPU_CNTL,  1 << 9);  in uvd_v4_2_start()
283 	WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);  in uvd_v4_2_start()
284 	WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);  in uvd_v4_2_start()
286 	WREG32(mmUVD_LMI_CTRL, 0x203108);  in uvd_v4_2_start()
289 	WREG32(mmUVD_MPC_CNTL, tmp | 0x10);  in uvd_v4_2_start()
291 	WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);  in uvd_v4_2_start()
292 	WREG32(mmUVD_MPC_SET_MUXA1, 0x0);  in uvd_v4_2_start()
293 	WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);  in uvd_v4_2_start()
294 	WREG32(mmUVD_MPC_SET_MUXB1, 0x0);  in uvd_v4_2_start()
295 	WREG32(mmUVD_MPC_SET_ALU, 0);  in uvd_v4_2_start()
296 	WREG32(mmUVD_MPC_SET_MUX, 0x88);  in uvd_v4_2_start()
346 	WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);  in uvd_v4_2_start()
349 	WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);  in uvd_v4_2_start()
352 	WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |  in uvd_v4_2_start()
356 	WREG32(mmUVD_RBC_RB_RPTR, 0x0);  in uvd_v4_2_start()
359 	WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));  in uvd_v4_2_start()
362 	WREG32(mmUVD_RBC_RB_BASE, ring->gpu_addr);  in uvd_v4_2_start()
384 	WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);  in uvd_v4_2_stop()
427 	WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |  in uvd_v4_2_stop()
431 	WREG32(mmUVD_STATUS, 0);  in uvd_v4_2_stop()
480 	WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);  in uvd_v4_2_ring_test_ring()
547 	WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);  in uvd_v4_2_mc_resume()
548 	WREG32(mmUVD_VCPU_CACHE_SIZE0, size);  in uvd_v4_2_mc_resume()
552 	WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr);  in uvd_v4_2_mc_resume()
553 	WREG32(mmUVD_VCPU_CACHE_SIZE1, size);  in uvd_v4_2_mc_resume()
558 	WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr);  in uvd_v4_2_mc_resume()
559 	WREG32(mmUVD_VCPU_CACHE_SIZE2, size);  in uvd_v4_2_mc_resume()
563 	WREG32(mmUVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));  in uvd_v4_2_mc_resume()
567 	WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));  in uvd_v4_2_mc_resume()
569 	WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);  in uvd_v4_2_mc_resume()
570 	WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);  in uvd_v4_2_mc_resume()
571 	WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);  in uvd_v4_2_mc_resume()
587 			WREG32(mmUVD_CGC_CTRL, data);  in uvd_v4_2_enable_mgcg()
596 			WREG32(mmUVD_CGC_CTRL, data);  in uvd_v4_2_enable_mgcg()
623 	WREG32(mmUVD_CGC_CTRL, tmp);  in uvd_v4_2_set_dcm()
700 				WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK   |  in uvd_v4_2_set_powergating_state()
711 				WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK   |  in uvd_v4_2_set_powergating_state()