Lines Matching refs:SOC15_REG_OFFSET
145 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); in soc15_uvd_ctx_rreg()
146 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); in soc15_uvd_ctx_rreg()
159 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); in soc15_uvd_ctx_wreg()
160 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); in soc15_uvd_ctx_wreg()
173 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); in soc15_didt_rreg()
174 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); in soc15_didt_rreg()
187 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); in soc15_didt_wreg()
188 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); in soc15_didt_wreg()
301 rom_index_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX_VG20); in soc15_read_bios_from_rom()
302 rom_data_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA_VG20); in soc15_read_bios_from_rom()
305 rom_index_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX); in soc15_read_bios_from_rom()
306 rom_data_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA); in soc15_read_bios_from_rom()
366 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) in soc15_get_register_value()
368 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)) in soc15_get_register_value()
428 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) || in soc15_program_register_sequence()
429 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) || in soc15_program_register_sequence()
430 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) || in soc15_program_register_sequence()
431 reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG)) in soc15_program_register_sequence()
848 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( in soc15_invalidate_hdp()
1435 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL)); in soc15_update_hdp_light_sleep()
1449 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data); in soc15_update_hdp_light_sleep()
1451 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); in soc15_update_hdp_light_sleep()
1459 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data); in soc15_update_hdp_light_sleep()
1467 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); in soc15_update_drm_clock_gating()
1489 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data); in soc15_update_drm_clock_gating()
1496 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); in soc15_update_drm_light_sleep()
1504 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data); in soc15_update_drm_light_sleep()
1512 def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0)); in soc15_update_rom_medium_grain_clock_gating()
1522 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data); in soc15_update_rom_medium_grain_clock_gating()
1588 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); in soc15_common_get_clockgating_state()
1593 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); in soc15_common_get_clockgating_state()
1598 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); in soc15_common_get_clockgating_state()
1603 data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0)); in soc15_common_get_clockgating_state()