Lines Matching refs:sdma_offsets
30 const u32 sdma_offsets[SDMA_MAX_INSTANCE] = variable
51 return (RREG32(DMA_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2; in si_dma_ring_get_wptr()
59 WREG32(DMA_RB_WPTR + sdma_offsets[me], in si_dma_ring_set_wptr()
121 rb_cntl = RREG32(DMA_RB_CNTL + sdma_offsets[i]); in si_dma_stop()
123 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); in si_dma_stop()
140 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0); in si_dma_start()
141 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); in si_dma_start()
149 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); in si_dma_start()
152 WREG32(DMA_RB_RPTR + sdma_offsets[i], 0); in si_dma_start()
153 WREG32(DMA_RB_WPTR + sdma_offsets[i], 0); in si_dma_start()
157 WREG32(DMA_RB_RPTR_ADDR_LO + sdma_offsets[i], lower_32_bits(rptr_addr)); in si_dma_start()
158 WREG32(DMA_RB_RPTR_ADDR_HI + sdma_offsets[i], upper_32_bits(rptr_addr) & 0xFF); in si_dma_start()
162 WREG32(DMA_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); in si_dma_start()
169 WREG32(DMA_IB_CNTL + sdma_offsets[i], ib_cntl); in si_dma_start()
171 dma_cntl = RREG32(DMA_CNTL + sdma_offsets[i]); in si_dma_start()
173 WREG32(DMA_CNTL + sdma_offsets[i], dma_cntl); in si_dma_start()
176 WREG32(DMA_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); in si_dma_start()
177 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl | DMA_RB_ENABLE); in si_dma_start()