Lines Matching refs:sdma_cntl
592 u32 sdma_cntl; in si_dma_set_trap_irq_state() local
598 sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
599 sdma_cntl &= ~TRAP_ENABLE; in si_dma_set_trap_irq_state()
600 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
603 sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
604 sdma_cntl |= TRAP_ENABLE; in si_dma_set_trap_irq_state()
605 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
614 sdma_cntl = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
615 sdma_cntl &= ~TRAP_ENABLE; in si_dma_set_trap_irq_state()
616 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
619 sdma_cntl = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
620 sdma_cntl |= TRAP_ENABLE; in si_dma_set_trap_irq_state()
621 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()