1755 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);  in si_vce_send_vcepll_ctlreq()
1760 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);  in si_vce_send_vcepll_ctlreq()
1772 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);  in si_vce_send_vcepll_ctlreq()
1788 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,  in si_set_vce_clocks()
1793 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_BYPASS_EN_MASK,  in si_set_vce_clocks()
1798 		WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK,  in si_set_vce_clocks()
1810 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK);  in si_set_vce_clocks()
1813 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_VCO_MODE_MASK,  in si_set_vce_clocks()
1817 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK,  in si_set_vce_clocks()
1819 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_SLEEP_MASK);  in si_set_vce_clocks()
1822 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK);  in si_set_vce_clocks()
1831 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_RESET_MASK, ~VCEPLL_RESET_MASK);  in si_set_vce_clocks()
1834 	WREG32_SMC_P(CG_VCEPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);  in si_set_vce_clocks()
1837 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_3,  in si_set_vce_clocks()
1842 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_REF_DIV_MASK);  in si_set_vce_clocks()
1845 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,  in si_set_vce_clocks()
1853 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK);  in si_set_vce_clocks()
1858 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_BYPASS_EN_MASK);  in si_set_vce_clocks()
1865 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,  in si_set_vce_clocks()