1528 	WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);  in si_uvd_send_upll_ctlreq()
1533 	WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);  in si_uvd_send_upll_ctlreq()
1545 	WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);  in si_uvd_send_upll_ctlreq()
1665 	WREG32_P(CG_UPLL_FUNC_CNTL_2,  in si_set_uvd_clocks()
1670 	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);  in si_set_uvd_clocks()
1684 	WREG32_P(CG_UPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK);  in si_set_uvd_clocks()
1687 	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);  in si_set_uvd_clocks()
1690 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);  in si_set_uvd_clocks()
1693 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);  in si_set_uvd_clocks()
1702 	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);  in si_set_uvd_clocks()
1705 	WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);  in si_set_uvd_clocks()
1708 	WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK);  in si_set_uvd_clocks()
1711 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);  in si_set_uvd_clocks()
1714 		WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9);  in si_set_uvd_clocks()
1716 		WREG32_P(CG_UPLL_FUNC_CNTL_4,  in si_set_uvd_clocks()
1721 	WREG32_P(CG_UPLL_FUNC_CNTL_2,  in si_set_uvd_clocks()
1729 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);  in si_set_uvd_clocks()
1734 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);  in si_set_uvd_clocks()
1741 	WREG32_P(CG_UPLL_FUNC_CNTL_2,  in si_set_uvd_clocks()