119 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_2_destroy_inst_ctx()
120 		release_firmware(adev->sdma.instance[i].fw);  in sdma_v5_2_destroy_inst_ctx()
121 		adev->sdma.instance[i].fw = NULL;  in sdma_v5_2_destroy_inst_ctx()
127 	memset((void*)adev->sdma.instance, 0,  in sdma_v5_2_destroy_inst_ctx()
169 	err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev);  in sdma_v5_2_init_microcode()
173 	err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[0]);  in sdma_v5_2_init_microcode()
177 	for (i = 1; i < adev->sdma.num_instances; i++) {  in sdma_v5_2_init_microcode()
180 			memcpy((void*)&adev->sdma.instance[i],  in sdma_v5_2_init_microcode()
181 			       (void*)&adev->sdma.instance[0],  in sdma_v5_2_init_microcode()
185 			err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);  in sdma_v5_2_init_microcode()
189 			err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[i]);  in sdma_v5_2_init_microcode()
199 		for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_2_init_microcode()
202 			info->fw = adev->sdma.instance[i].fw;  in sdma_v5_2_init_microcode()
333 	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);  in sdma_v5_2_ring_insert_nop()  local
337 		if (sdma && sdma->burst_nop && (i == 0))  in sdma_v5_2_ring_insert_nop()
458 	struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;  in sdma_v5_2_gfx_stop()
459 	struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;  in sdma_v5_2_gfx_stop()
460 	struct amdgpu_ring *sdma2 = &adev->sdma.instance[2].ring;  in sdma_v5_2_gfx_stop()
461 	struct amdgpu_ring *sdma3 = &adev->sdma.instance[3].ring;  in sdma_v5_2_gfx_stop()
471 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_2_gfx_stop()
535 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_2_ctx_switch_enable()
570 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_2_enable()
598 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_2_gfx_resume()
599 		ring = &adev->sdma.instance[i].ring;  in sdma_v5_2_gfx_resume()
772 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_2_load_microcode()
773 		if (!adev->sdma.instance[i].fw)  in sdma_v5_2_load_microcode()
776 		hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;  in sdma_v5_2_load_microcode()
781 			(adev->sdma.instance[i].fw->data +  in sdma_v5_2_load_microcode()
792 		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);  in sdma_v5_2_load_microcode()
1073 	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);  in sdma_v5_2_ring_pad_ib()  local
1079 		if (sdma && sdma->burst_nop && (i == 0))  in sdma_v5_2_ring_pad_ib()
1169 		adev->sdma.num_instances = 4;  in sdma_v5_2_early_init()
1172 		adev->sdma.num_instances = 2;  in sdma_v5_2_early_init()
1227 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_2_sw_init()
1230 				      &adev->sdma.trap_irq);  in sdma_v5_2_sw_init()
1241 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_2_sw_init()
1242 		ring = &adev->sdma.instance[i].ring;  in sdma_v5_2_sw_init()
1255 				     &adev->sdma.trap_irq,  in sdma_v5_2_sw_init()
1270 	for (i = 0; i < adev->sdma.num_instances; i++)  in sdma_v5_2_sw_fini()
1271 		amdgpu_ring_fini(&adev->sdma.instance[i].ring);  in sdma_v5_2_sw_fini()
1322 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_2_is_idle()
1429 			amdgpu_fence_process(&adev->sdma.instance[0].ring);  in sdma_v5_2_process_trap_irq()
1445 			amdgpu_fence_process(&adev->sdma.instance[1].ring);  in sdma_v5_2_process_trap_irq()
1461 			amdgpu_fence_process(&adev->sdma.instance[2].ring);  in sdma_v5_2_process_trap_irq()
1477 			amdgpu_fence_process(&adev->sdma.instance[3].ring);  in sdma_v5_2_process_trap_irq()
1507 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_2_update_medium_grain_clock_gating()
1540 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_2_update_medium_grain_light_sleep()
1660 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_2_set_ring_funcs()
1661 		adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs;  in sdma_v5_2_set_ring_funcs()
1662 		adev->sdma.instance[i].ring.me = i;  in sdma_v5_2_set_ring_funcs()
1677 	adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +  in sdma_v5_2_set_irq_funcs()
1678 					adev->sdma.num_instances;  in sdma_v5_2_set_irq_funcs()
1679 	adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs;  in sdma_v5_2_set_irq_funcs()
1680 	adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs;  in sdma_v5_2_set_irq_funcs()
1748 		adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;  in sdma_v5_2_set_buffer_funcs()
1765 		for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_2_set_vm_pte_funcs()
1767 				&adev->sdma.instance[i].ring.sched;  in sdma_v5_2_set_vm_pte_funcs()
1769 		adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;  in sdma_v5_2_set_vm_pte_funcs()