354 				   struct amdgpu_ib *ib,  in sdma_v5_2_ring_emit_ib()  argument
373 	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);  in sdma_v5_2_ring_emit_ib()
374 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));  in sdma_v5_2_ring_emit_ib()
375 	amdgpu_ring_write(ring, ib->length_dw);  in sdma_v5_2_ring_emit_ib()
915 	struct amdgpu_ib ib;  in sdma_v5_2_ring_test_ib()  local
931 	memset(&ib, 0, sizeof(ib));  in sdma_v5_2_ring_test_ib()
932 	r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);  in sdma_v5_2_ring_test_ib()
938 	ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |  in sdma_v5_2_ring_test_ib()
940 	ib.ptr[1] = lower_32_bits(gpu_addr);  in sdma_v5_2_ring_test_ib()
941 	ib.ptr[2] = upper_32_bits(gpu_addr);  in sdma_v5_2_ring_test_ib()
942 	ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);  in sdma_v5_2_ring_test_ib()
943 	ib.ptr[4] = 0xDEADBEEF;  in sdma_v5_2_ring_test_ib()
944 	ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);  in sdma_v5_2_ring_test_ib()
945 	ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);  in sdma_v5_2_ring_test_ib()
946 	ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);  in sdma_v5_2_ring_test_ib()
947 	ib.length_dw = 8;  in sdma_v5_2_ring_test_ib()
949 	r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);  in sdma_v5_2_ring_test_ib()
969 	amdgpu_ib_free(adev, &ib, NULL);  in sdma_v5_2_ring_test_ib()
987 static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib,  in sdma_v5_2_vm_copy_pte()  argument
993 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |  in sdma_v5_2_vm_copy_pte()
995 	ib->ptr[ib->length_dw++] = bytes - 1;  in sdma_v5_2_vm_copy_pte()
996 	ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */  in sdma_v5_2_vm_copy_pte()
997 	ib->ptr[ib->length_dw++] = lower_32_bits(src);  in sdma_v5_2_vm_copy_pte()
998 	ib->ptr[ib->length_dw++] = upper_32_bits(src);  in sdma_v5_2_vm_copy_pte()
999 	ib->ptr[ib->length_dw++] = lower_32_bits(pe);  in sdma_v5_2_vm_copy_pte()
1000 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);  in sdma_v5_2_vm_copy_pte()
1016 static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,  in sdma_v5_2_vm_write_pte()  argument
1022 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |  in sdma_v5_2_vm_write_pte()
1024 	ib->ptr[ib->length_dw++] = lower_32_bits(pe);  in sdma_v5_2_vm_write_pte()
1025 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);  in sdma_v5_2_vm_write_pte()
1026 	ib->ptr[ib->length_dw++] = ndw - 1;  in sdma_v5_2_vm_write_pte()
1028 		ib->ptr[ib->length_dw++] = lower_32_bits(value);  in sdma_v5_2_vm_write_pte()
1029 		ib->ptr[ib->length_dw++] = upper_32_bits(value);  in sdma_v5_2_vm_write_pte()
1046 static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib,  in sdma_v5_2_vm_set_pte_pde()  argument
1052 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);  in sdma_v5_2_vm_set_pte_pde()
1053 	ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */  in sdma_v5_2_vm_set_pte_pde()
1054 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);  in sdma_v5_2_vm_set_pte_pde()
1055 	ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */  in sdma_v5_2_vm_set_pte_pde()
1056 	ib->ptr[ib->length_dw++] = upper_32_bits(flags);  in sdma_v5_2_vm_set_pte_pde()
1057 	ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */  in sdma_v5_2_vm_set_pte_pde()
1058 	ib->ptr[ib->length_dw++] = upper_32_bits(addr);  in sdma_v5_2_vm_set_pte_pde()
1059 	ib->ptr[ib->length_dw++] = incr; /* increment size */  in sdma_v5_2_vm_set_pte_pde()
1060 	ib->ptr[ib->length_dw++] = 0;  in sdma_v5_2_vm_set_pte_pde()
1061 	ib->ptr[ib->length_dw++] = count - 1; /* number of entries */  in sdma_v5_2_vm_set_pte_pde()
1071 static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)  in sdma_v5_2_ring_pad_ib()  argument
1077 	pad_count = (-ib->length_dw) & 0x7;  in sdma_v5_2_ring_pad_ib()
1080 			ib->ptr[ib->length_dw++] =  in sdma_v5_2_ring_pad_ib()
1084 			ib->ptr[ib->length_dw++] =  in sdma_v5_2_ring_pad_ib()
1695 static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib,  in sdma_v5_2_emit_copy_buffer()  argument
1701 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |  in sdma_v5_2_emit_copy_buffer()
1704 	ib->ptr[ib->length_dw++] = byte_count - 1;  in sdma_v5_2_emit_copy_buffer()
1705 	ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */  in sdma_v5_2_emit_copy_buffer()
1706 	ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);  in sdma_v5_2_emit_copy_buffer()
1707 	ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);  in sdma_v5_2_emit_copy_buffer()
1708 	ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);  in sdma_v5_2_emit_copy_buffer()
1709 	ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);  in sdma_v5_2_emit_copy_buffer()
1722 static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib,  in sdma_v5_2_emit_fill_buffer()  argument
1727 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);  in sdma_v5_2_emit_fill_buffer()
1728 	ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);  in sdma_v5_2_emit_fill_buffer()
1729 	ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);  in sdma_v5_2_emit_fill_buffer()
1730 	ib->ptr[ib->length_dw++] = src_data;  in sdma_v5_2_emit_fill_buffer()
1731 	ib->ptr[ib->length_dw++] = byte_count - 1;  in sdma_v5_2_emit_fill_buffer()