401 				   struct amdgpu_ib *ib,  in sdma_v5_0_ring_emit_ib()  argument
432 	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);  in sdma_v5_0_ring_emit_ib()
433 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));  in sdma_v5_0_ring_emit_ib()
434 	amdgpu_ring_write(ring, ib->length_dw);  in sdma_v5_0_ring_emit_ib()
969 	struct amdgpu_ib ib;  in sdma_v5_0_ring_test_ib()  local
985 	memset(&ib, 0, sizeof(ib));  in sdma_v5_0_ring_test_ib()
987 					AMDGPU_IB_POOL_DIRECT, &ib);  in sdma_v5_0_ring_test_ib()
993 	ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |  in sdma_v5_0_ring_test_ib()
995 	ib.ptr[1] = lower_32_bits(gpu_addr);  in sdma_v5_0_ring_test_ib()
996 	ib.ptr[2] = upper_32_bits(gpu_addr);  in sdma_v5_0_ring_test_ib()
997 	ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);  in sdma_v5_0_ring_test_ib()
998 	ib.ptr[4] = 0xDEADBEEF;  in sdma_v5_0_ring_test_ib()
999 	ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);  in sdma_v5_0_ring_test_ib()
1000 	ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);  in sdma_v5_0_ring_test_ib()
1001 	ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);  in sdma_v5_0_ring_test_ib()
1002 	ib.length_dw = 8;  in sdma_v5_0_ring_test_ib()
1004 	r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);  in sdma_v5_0_ring_test_ib()
1024 	amdgpu_ib_free(adev, &ib, NULL);  in sdma_v5_0_ring_test_ib()
1042 static void sdma_v5_0_vm_copy_pte(struct amdgpu_ib *ib,  in sdma_v5_0_vm_copy_pte()  argument
1048 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |  in sdma_v5_0_vm_copy_pte()
1050 	ib->ptr[ib->length_dw++] = bytes - 1;  in sdma_v5_0_vm_copy_pte()
1051 	ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */  in sdma_v5_0_vm_copy_pte()
1052 	ib->ptr[ib->length_dw++] = lower_32_bits(src);  in sdma_v5_0_vm_copy_pte()
1053 	ib->ptr[ib->length_dw++] = upper_32_bits(src);  in sdma_v5_0_vm_copy_pte()
1054 	ib->ptr[ib->length_dw++] = lower_32_bits(pe);  in sdma_v5_0_vm_copy_pte()
1055 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);  in sdma_v5_0_vm_copy_pte()
1071 static void sdma_v5_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,  in sdma_v5_0_vm_write_pte()  argument
1077 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |  in sdma_v5_0_vm_write_pte()
1079 	ib->ptr[ib->length_dw++] = lower_32_bits(pe);  in sdma_v5_0_vm_write_pte()
1080 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);  in sdma_v5_0_vm_write_pte()
1081 	ib->ptr[ib->length_dw++] = ndw - 1;  in sdma_v5_0_vm_write_pte()
1083 		ib->ptr[ib->length_dw++] = lower_32_bits(value);  in sdma_v5_0_vm_write_pte()
1084 		ib->ptr[ib->length_dw++] = upper_32_bits(value);  in sdma_v5_0_vm_write_pte()
1101 static void sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib *ib,  in sdma_v5_0_vm_set_pte_pde()  argument
1107 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);  in sdma_v5_0_vm_set_pte_pde()
1108 	ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */  in sdma_v5_0_vm_set_pte_pde()
1109 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);  in sdma_v5_0_vm_set_pte_pde()
1110 	ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */  in sdma_v5_0_vm_set_pte_pde()
1111 	ib->ptr[ib->length_dw++] = upper_32_bits(flags);  in sdma_v5_0_vm_set_pte_pde()
1112 	ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */  in sdma_v5_0_vm_set_pte_pde()
1113 	ib->ptr[ib->length_dw++] = upper_32_bits(addr);  in sdma_v5_0_vm_set_pte_pde()
1114 	ib->ptr[ib->length_dw++] = incr; /* increment size */  in sdma_v5_0_vm_set_pte_pde()
1115 	ib->ptr[ib->length_dw++] = 0;  in sdma_v5_0_vm_set_pte_pde()
1116 	ib->ptr[ib->length_dw++] = count - 1; /* number of entries */  in sdma_v5_0_vm_set_pte_pde()
1125 static void sdma_v5_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)  in sdma_v5_0_ring_pad_ib()  argument
1131 	pad_count = (-ib->length_dw) & 0x7;  in sdma_v5_0_ring_pad_ib()
1134 			ib->ptr[ib->length_dw++] =  in sdma_v5_0_ring_pad_ib()
1138 			ib->ptr[ib->length_dw++] =  in sdma_v5_0_ring_pad_ib()
1698 static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib,  in sdma_v5_0_emit_copy_buffer()  argument
1704 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |  in sdma_v5_0_emit_copy_buffer()
1707 	ib->ptr[ib->length_dw++] = byte_count - 1;  in sdma_v5_0_emit_copy_buffer()
1708 	ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */  in sdma_v5_0_emit_copy_buffer()
1709 	ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);  in sdma_v5_0_emit_copy_buffer()
1710 	ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);  in sdma_v5_0_emit_copy_buffer()
1711 	ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);  in sdma_v5_0_emit_copy_buffer()
1712 	ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);  in sdma_v5_0_emit_copy_buffer()
1725 static void sdma_v5_0_emit_fill_buffer(struct amdgpu_ib *ib,  in sdma_v5_0_emit_fill_buffer()  argument
1730 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);  in sdma_v5_0_emit_fill_buffer()
1731 	ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);  in sdma_v5_0_emit_fill_buffer()
1732 	ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);  in sdma_v5_0_emit_fill_buffer()
1733 	ib->ptr[ib->length_dw++] = src_data;  in sdma_v5_0_emit_fill_buffer()
1734 	ib->ptr[ib->length_dw++] = byte_count - 1;  in sdma_v5_0_emit_fill_buffer()