Lines Matching full:sdma
225 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_init_microcode()
230 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); in sdma_v5_0_init_microcode()
233 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); in sdma_v5_0_init_microcode()
236 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; in sdma_v5_0_init_microcode()
237 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); in sdma_v5_0_init_microcode()
238 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); in sdma_v5_0_init_microcode()
239 if (adev->sdma.instance[i].feature_version >= 20) in sdma_v5_0_init_microcode()
240 adev->sdma.instance[i].burst_nop = true; in sdma_v5_0_init_microcode()
247 info->fw = adev->sdma.instance[i].fw; in sdma_v5_0_init_microcode()
256 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_init_microcode()
257 release_firmware(adev->sdma.instance[i].fw); in sdma_v5_0_init_microcode()
258 adev->sdma.instance[i].fw = NULL; in sdma_v5_0_init_microcode()
380 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); in sdma_v5_0_ring_insert_nop() local
384 if (sdma && sdma->burst_nop && (i == 0)) in sdma_v5_0_ring_insert_nop()
520 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; in sdma_v5_0_gfx_stop()
521 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; in sdma_v5_0_gfx_stop()
529 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_gfx_stop()
588 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_ctx_switch_enable()
630 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_enable()
658 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_gfx_resume()
659 ring = &adev->sdma.instance[i].ring; in sdma_v5_0_gfx_resume()
813 * sdma_v5_0_load_microcode - load the sDMA ME ucode
830 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_load_microcode()
831 if (!adev->sdma.instance[i].fw) in sdma_v5_0_load_microcode()
834 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; in sdma_v5_0_load_microcode()
839 (adev->sdma.instance[i].fw->data + in sdma_v5_0_load_microcode()
850 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); in sdma_v5_0_load_microcode()
885 /* enable sdma ring preemption */ in sdma_v5_0_start()
1040 * Update PTEs by copying them from the GART using sDMA (NAVI10).
1069 * Update PTEs by writing them manually using sDMA (NAVI10).
1090 * sdma_v5_0_vm_set_pte_pde - update the page tables using sDMA
1099 * Update the page tables using sDMA (NAVI10).
1127 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); in sdma_v5_0_ring_pad_ib() local
1133 if (sdma && sdma->burst_nop && (i == 0)) in sdma_v5_0_ring_pad_ib()
1170 * sdma_v5_0_ring_emit_vm_flush - vm flush using sDMA
1176 * using sDMA (NAVI10).
1221 adev->sdma.num_instances = 2; in sdma_v5_0_early_init()
1238 /* SDMA trap event */ in sdma_v5_0_sw_init()
1241 &adev->sdma.trap_irq); in sdma_v5_0_sw_init()
1245 /* SDMA trap event */ in sdma_v5_0_sw_init()
1248 &adev->sdma.trap_irq); in sdma_v5_0_sw_init()
1254 DRM_ERROR("Failed to load sdma firmware!\n"); in sdma_v5_0_sw_init()
1258 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_sw_init()
1259 ring = &adev->sdma.instance[i].ring; in sdma_v5_0_sw_init()
1263 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, in sdma_v5_0_sw_init()
1270 sprintf(ring->name, "sdma%d", i); in sdma_v5_0_sw_init()
1272 &adev->sdma.trap_irq, in sdma_v5_0_sw_init()
1289 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_sw_fini()
1290 release_firmware(adev->sdma.instance[i].fw); in sdma_v5_0_sw_fini()
1291 adev->sdma.instance[i].fw = NULL; in sdma_v5_0_sw_fini()
1293 amdgpu_ring_fini(&adev->sdma.instance[i].ring); in sdma_v5_0_sw_fini()
1343 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_is_idle()
1449 DRM_DEBUG("IH: SDMA trap\n"); in sdma_v5_0_process_trap_irq()
1454 amdgpu_fence_process(&adev->sdma.instance[0].ring); in sdma_v5_0_process_trap_irq()
1470 amdgpu_fence_process(&adev->sdma.instance[1].ring); in sdma_v5_0_process_trap_irq()
1500 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_update_medium_grain_clock_gating()
1502 /* Enable sdma clock gating */ in sdma_v5_0_update_medium_grain_clock_gating()
1515 /* Disable sdma clock gating */ in sdma_v5_0_update_medium_grain_clock_gating()
1537 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_update_medium_grain_light_sleep()
1539 /* Enable sdma mem light sleep */ in sdma_v5_0_update_medium_grain_light_sleep()
1546 /* Disable sdma mem light sleep */ in sdma_v5_0_update_medium_grain_light_sleep()
1663 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_set_ring_funcs()
1664 adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs; in sdma_v5_0_set_ring_funcs()
1665 adev->sdma.instance[i].ring.me = i; in sdma_v5_0_set_ring_funcs()
1680 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + in sdma_v5_0_set_irq_funcs()
1681 adev->sdma.num_instances; in sdma_v5_0_set_irq_funcs()
1682 adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs; in sdma_v5_0_set_irq_funcs()
1683 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs; in sdma_v5_0_set_irq_funcs()
1687 * sdma_v5_0_emit_copy_buffer - copy buffer using the sDMA engine
1716 * sdma_v5_0_emit_fill_buffer - fill buffer using the sDMA engine
1751 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; in sdma_v5_0_set_buffer_funcs()
1768 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_set_vm_pte_funcs()
1770 &adev->sdma.instance[i].ring.sched; in sdma_v5_0_set_vm_pte_funcs()
1772 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; in sdma_v5_0_set_vm_pte_funcs()