47 	mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
48 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
49 	mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
50 	mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
51 	mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
52 	mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
53 	mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
54 	mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
55 	mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
56 	mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
57 	mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
58 	mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
59 	mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
60 	mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
61 	mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
62 	mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
63 	mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
64 	mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
65 	mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
66 	mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
67 	mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
68 	mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
69 	mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
70 	mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
71 	mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
72 	mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
73 	mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
74 	mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
75 	mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
76 	mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
77 	mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
78 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
79 	mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
80 	mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
81 	mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
82 	mmPCIE_INDEX, 0xffffffff, 0x0140001c,
83 	mmPCIE_DATA, 0x000f0000, 0x00000000,
84 	mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
85 	mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
86 	mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
87 	mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
88 	mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104,
89 	mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
90 	mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
91 	mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
92 	mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
93 	mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100,
97 	mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
98 	mmDB_DEBUG2, 0xf00fffff, 0x00000400,
99 	mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
100 	mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
101 	mmFBC_MISC, 0x1f311fff, 0x12300000,
102 	mmHDMI_CONTROL, 0x31000111, 0x00000011,
103 	mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
104 	mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
105 	mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
106 	mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
107 	mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
108 	mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
109 	mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
110 	mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
111 	mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
112 	mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
113 	mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
114 	mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
115 	mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
116 	mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff,
117 	mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
118 	mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
119 	mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
120 	mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
121 	mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
125 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
126 	mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a,
127 	mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e,
128 	mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
129 	mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
130 	mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
131 	mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
132 	mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF,
133 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
134 	mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x00000009,
138 	mmRLC_CGTT_MGCG_OVERRIDE,   0xffffffff, 0xffffffff,
139 	mmGRBM_GFX_INDEX,           0xffffffff, 0xe0000000,
140 	mmCB_CGTT_SCLK_CTRL,        0xffffffff, 0x00000100,
141 	mmCGTT_BCI_CLK_CTRL,        0xffffffff, 0x00000100,
142 	mmCGTT_CP_CLK_CTRL,         0xffffffff, 0x00000100,
143 	mmCGTT_CPC_CLK_CTRL,        0xffffffff, 0x00000100,
144 	mmCGTT_CPF_CLK_CTRL,        0xffffffff, 0x40000100,
145 	mmCGTT_DRM_CLK_CTRL0,       0xffffffff, 0x00600100,
146 	mmCGTT_GDS_CLK_CTRL,        0xffffffff, 0x00000100,
147 	mmCGTT_IA_CLK_CTRL,         0xffffffff, 0x06000100,
148 	mmCGTT_PA_CLK_CTRL,         0xffffffff, 0x00000100,
149 	mmCGTT_WD_CLK_CTRL,         0xffffffff, 0x06000100,
150 	mmCGTT_PC_CLK_CTRL,         0xffffffff, 0x00000100,
151 	mmCGTT_RLC_CLK_CTRL,        0xffffffff, 0x00000100,
152 	mmCGTT_SC_CLK_CTRL,         0xffffffff, 0x00000100,
153 	mmCGTT_SPI_CLK_CTRL,        0xffffffff, 0x00000100,
154 	mmCGTT_SQ_CLK_CTRL,         0xffffffff, 0x00000100,
155 	mmCGTT_SQG_CLK_CTRL,        0xffffffff, 0x00000100,
156 	mmCGTT_SX_CLK_CTRL0,        0xffffffff, 0x00000100,
157 	mmCGTT_SX_CLK_CTRL1,        0xffffffff, 0x00000100,
158 	mmCGTT_SX_CLK_CTRL2,        0xffffffff, 0x00000100,
159 	mmCGTT_SX_CLK_CTRL3,        0xffffffff, 0x00000100,
160 	mmCGTT_SX_CLK_CTRL4,        0xffffffff, 0x00000100,
161 	mmCGTT_TCI_CLK_CTRL,        0xffffffff, 0x00000100,
162 	mmCGTT_TCP_CLK_CTRL,        0xffffffff, 0x00000100,
163 	mmCGTT_VGT_CLK_CTRL,        0xffffffff, 0x06000100,
164 	mmDB_CGTT_CLK_CTRL_0,       0xffffffff, 0x00000100,
165 	mmTA_CGTT_CTRL,             0xffffffff, 0x00000100,
166 	mmTCA_CGTT_SCLK_CTRL,       0xffffffff, 0x00000100,
167 	mmTCC_CGTT_SCLK_CTRL,       0xffffffff, 0x00000100,
168 	mmTD_CGTT_CTRL,             0xffffffff, 0x00000100,
169 	mmGRBM_GFX_INDEX,           0xffffffff, 0xe0000000,
170 	mmCGTS_CU0_SP0_CTRL_REG,    0xffffffff, 0x00010000,
171 	mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
172 	mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
173 	mmCGTS_CU0_SP1_CTRL_REG,    0xffffffff, 0x00060005,
174 	mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
175 	mmCGTS_CU1_SP0_CTRL_REG,    0xffffffff, 0x00010000,
176 	mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
177 	mmCGTS_CU1_TA_CTRL_REG,     0xffffffff, 0x00040007,
178 	mmCGTS_CU1_SP1_CTRL_REG,    0xffffffff, 0x00060005,
179 	mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
180 	mmCGTS_CU2_SP0_CTRL_REG,    0xffffffff, 0x00010000,
181 	mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
182 	mmCGTS_CU2_TA_CTRL_REG,     0xffffffff, 0x00040007,
183 	mmCGTS_CU2_SP1_CTRL_REG,    0xffffffff, 0x00060005,
184 	mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
185 	mmCGTS_CU3_SP0_CTRL_REG,    0xffffffff, 0x00010000,
186 	mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
187 	mmCGTS_CU3_TA_CTRL_REG,     0xffffffff, 0x00040007,
188 	mmCGTS_CU3_SP1_CTRL_REG,    0xffffffff, 0x00060005,
189 	mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
190 	mmCGTS_CU4_SP0_CTRL_REG,    0xffffffff, 0x00010000,
191 	mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
192 	mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
193 	mmCGTS_CU4_SP1_CTRL_REG,    0xffffffff, 0x00060005,
194 	mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
195 	mmCGTS_CU5_SP0_CTRL_REG,    0xffffffff, 0x00010000,
196 	mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
197 	mmCGTS_CU5_TA_CTRL_REG,     0xffffffff, 0x00040007,
198 	mmCGTS_CU5_SP1_CTRL_REG,    0xffffffff, 0x00060005,
199 	mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
200 	mmCGTS_CU6_SP0_CTRL_REG,    0xffffffff, 0x00010000,
201 	mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
202 	mmCGTS_CU6_TA_CTRL_REG,     0xffffffff, 0x00040007,
203 	mmCGTS_CU6_SP1_CTRL_REG,    0xffffffff, 0x00060005,
204 	mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
205 	mmCGTS_CU7_SP0_CTRL_REG,    0xffffffff, 0x00010000,
206 	mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
207 	mmCGTS_CU7_TA_CTRL_REG,     0xffffffff, 0x00040007,
208 	mmCGTS_CU7_SP1_CTRL_REG,    0xffffffff, 0x00060005,
209 	mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
210 	mmCGTS_SM_CTRL_REG,         0xffffffff, 0x96e00200,
211 	mmCP_RB_WPTR_POLL_CNTL,     0xffffffff, 0x00900100,
212 	mmRLC_CGCG_CGLS_CTRL,       0xffffffff, 0x0020003c,
213 	mmPCIE_INDEX,               0xffffffff, 0x0140001c,
214 	mmPCIE_DATA,                0x000f0000, 0x00000000,
215 	mmSMC_IND_INDEX_4,          0xffffffff, 0xC060000C,
216 	mmSMC_IND_DATA_4,           0xc0000fff, 0x00000100,
217 	mmXDMA_CLOCK_GATING_CNTL,   0xffffffff, 0x00000100,
218 	mmXDMA_MEM_POWER_CNTL,      0x00000101, 0x00000000,
219 	mmMC_MEM_POWER_LS,          0xffffffff, 0x00000104,
220 	mmCGTT_DRM_CLK_CTRL0,       0xff000fff, 0x00000100,
221 	mmHDP_XDP_CGTT_BLK_CTRL,    0xc0000fff, 0x00000104,
222 	mmCP_MEM_SLP_CNTL,          0x00000001, 0x00000001,
223 	mmSDMA0_CLK_CTRL,           0xff000ff0, 0x00000100,
224 	mmSDMA1_CLK_CTRL,           0xff000ff0, 0x00000100,
228 	mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
229 	mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
230 	mmDB_DEBUG2, 0xf00fffff, 0x00000400,
231 	mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
232 	mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
233 	mmFBC_MISC, 0x1f311fff, 0x12300000,
234 	mmGB_GPU_ID, 0x0000000f, 0x00000000,
235 	mmHDMI_CONTROL, 0x31000111, 0x00000011,
236 	mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
237 	mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028,
238 	mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991,
239 	mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
240 	mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
241 	mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
242 	mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
243 	mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
244 	mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
245 	mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
246 	mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
247 	mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
248 	mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
249 	mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
250 	mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
251 	mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
252 	mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
253 	mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
254 	mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
255 	mmTCC_CTRL, 0x00100000, 0xf31fff7f,
256 	mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
257 	mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,
258 	mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
259 	mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
260 	mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
261 	mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
262 	mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
263 	mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
264 	mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
268 	mmGRBM_GFX_INDEX,               0xffffffff, 0xe0000000,
269 	mmPA_SC_RASTER_CONFIG,          0xffffffff, 0x16000012,
270 	mmPA_SC_RASTER_CONFIG_1,        0xffffffff, 0x0000002A,
271 	mmGB_ADDR_CONFIG,               0xffffffff, 0x22011002,
272 	mmSPI_RESOURCE_RESERVE_CU_0,    0xffffffff, 0x00000800,
273 	mmSPI_RESOURCE_RESERVE_CU_1,    0xffffffff, 0x00000800,
274 	mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
279 	switch (adev->asic_type) {  in xgpu_vi_init_golden_registers()
327 	/*Wait for RCV_MSG_VALID to be 0*/  in xgpu_vi_mailbox_send_ack()
330 		if (timeout <= 0) {  in xgpu_vi_mailbox_send_ack()
335 		timeout -=1;  in xgpu_vi_mailbox_send_ack()
347 			    TRN_MSG_VALID, val ? 1 : 0);  in xgpu_vi_mailbox_set_valid()
374 			return -ENOENT;  in xgpu_vi_mailbox_rcv_msg()
379 		return -ENOENT;  in xgpu_vi_mailbox_rcv_msg()
384 	return 0;  in xgpu_vi_mailbox_rcv_msg()
389 	int r = 0, timeout = VI_MAILBOX_TIMEDOUT;  in xgpu_vi_poll_ack()
395 		if (timeout <= 0) {  in xgpu_vi_poll_ack()
397 			r = -ETIME;  in xgpu_vi_poll_ack()
401 		timeout -= 5;  in xgpu_vi_poll_ack()
411 	int r = 0, timeout = VI_MAILBOX_TIMEDOUT;  in xgpu_vi_poll_msg()
415 		if (timeout <= 0) {  in xgpu_vi_poll_msg()
417 			r = -ETIME;  in xgpu_vi_poll_msg()
421 		timeout -= 5;  in xgpu_vi_poll_msg()
454 	return 0;  in xgpu_vi_send_access_requests()
480 	int r = 0;  in xgpu_vi_release_full_gpu_access()
494 	return 0;  in xgpu_vi_mailbox_ack_irq()
505 			    (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0);  in xgpu_vi_set_mailbox_ack_irq()
508 	return 0;  in xgpu_vi_set_mailbox_ack_irq()
535 			    (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0);  in xgpu_vi_set_mailbox_rcv_irq()
538 	return 0;  in xgpu_vi_set_mailbox_rcv_irq()
547 	/* trigger gpu-reset by hypervisor only if TDR disbaled */  in xgpu_vi_mailbox_rcv_irq()
554 			schedule_work(&adev->virt.flr_work);  in xgpu_vi_mailbox_rcv_irq()
557 	return 0;  in xgpu_vi_mailbox_rcv_irq()
572 	adev->virt.ack_irq.num_types = 1;  in xgpu_vi_mailbox_set_irq_funcs()
573 	adev->virt.ack_irq.funcs = &xgpu_vi_mailbox_ack_irq_funcs;  in xgpu_vi_mailbox_set_irq_funcs()
574 	adev->virt.rcv_irq.num_types = 1;  in xgpu_vi_mailbox_set_irq_funcs()
575 	adev->virt.rcv_irq.funcs = &xgpu_vi_mailbox_rcv_irq_funcs;  in xgpu_vi_mailbox_set_irq_funcs()
582 	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 135, &adev->virt.rcv_irq);  in xgpu_vi_mailbox_add_irq_id()
586 	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 138, &adev->virt.ack_irq);  in xgpu_vi_mailbox_add_irq_id()
588 		amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);  in xgpu_vi_mailbox_add_irq_id()
592 	return 0;  in xgpu_vi_mailbox_add_irq_id()
599 	r = amdgpu_irq_get(adev, &adev->virt.rcv_irq, 0);  in xgpu_vi_mailbox_get_irq()
602 	r = amdgpu_irq_get(adev, &adev->virt.ack_irq, 0);  in xgpu_vi_mailbox_get_irq()
604 		amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);  in xgpu_vi_mailbox_get_irq()
608 	INIT_WORK(&adev->virt.flr_work, xgpu_vi_mailbox_flr_work);  in xgpu_vi_mailbox_get_irq()
610 	return 0;  in xgpu_vi_mailbox_get_irq()
615 	amdgpu_irq_put(adev, &adev->virt.ack_irq, 0);  in xgpu_vi_mailbox_put_irq()
616 	amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);  in xgpu_vi_mailbox_put_irq()