Lines Matching full:ring
65 * Set ring and irq function pointers
89 struct amdgpu_ring *ring; in jpeg_v2_0_sw_init() local
106 ring = &adev->jpeg.inst->ring_dec; in jpeg_v2_0_sw_init()
107 ring->use_doorbell = true; in jpeg_v2_0_sw_init()
108 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1; in jpeg_v2_0_sw_init()
109 sprintf(ring->name, "jpeg_dec"); in jpeg_v2_0_sw_init()
110 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, in jpeg_v2_0_sw_init()
151 struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec; in jpeg_v2_0_hw_init() local
154 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, in jpeg_v2_0_hw_init()
157 r = amdgpu_ring_test_helper(ring); in jpeg_v2_0_hw_init()
169 * Stop the JPEG block, mark ring as not ready any more
332 struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec; in jpeg_v2_0_start() local
360 lower_32_bits(ring->gpu_addr)); in jpeg_v2_0_start()
362 upper_32_bits(ring->gpu_addr)); in jpeg_v2_0_start()
366 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4); in jpeg_v2_0_start()
367 ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); in jpeg_v2_0_start()
405 * @ring: amdgpu_ring pointer
409 static uint64_t jpeg_v2_0_dec_ring_get_rptr(struct amdgpu_ring *ring) in jpeg_v2_0_dec_ring_get_rptr() argument
411 struct amdgpu_device *adev = ring->adev; in jpeg_v2_0_dec_ring_get_rptr()
419 * @ring: amdgpu_ring pointer
423 static uint64_t jpeg_v2_0_dec_ring_get_wptr(struct amdgpu_ring *ring) in jpeg_v2_0_dec_ring_get_wptr() argument
425 struct amdgpu_device *adev = ring->adev; in jpeg_v2_0_dec_ring_get_wptr()
427 if (ring->use_doorbell) in jpeg_v2_0_dec_ring_get_wptr()
428 return adev->wb.wb[ring->wptr_offs]; in jpeg_v2_0_dec_ring_get_wptr()
436 * @ring: amdgpu_ring pointer
440 static void jpeg_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring) in jpeg_v2_0_dec_ring_set_wptr() argument
442 struct amdgpu_device *adev = ring->adev; in jpeg_v2_0_dec_ring_set_wptr()
444 if (ring->use_doorbell) { in jpeg_v2_0_dec_ring_set_wptr()
445 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in jpeg_v2_0_dec_ring_set_wptr()
446 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); in jpeg_v2_0_dec_ring_set_wptr()
448 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); in jpeg_v2_0_dec_ring_set_wptr()
455 * @ring: amdgpu_ring pointer
457 * Write a start command to the ring.
459 void jpeg_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring) in jpeg_v2_0_dec_ring_insert_start() argument
461 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_insert_start()
463 amdgpu_ring_write(ring, 0x68e04); in jpeg_v2_0_dec_ring_insert_start()
465 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in jpeg_v2_0_dec_ring_insert_start()
467 amdgpu_ring_write(ring, 0x80010000); in jpeg_v2_0_dec_ring_insert_start()
473 * @ring: amdgpu_ring pointer
475 * Write a end command to the ring.
477 void jpeg_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring) in jpeg_v2_0_dec_ring_insert_end() argument
479 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_insert_end()
481 amdgpu_ring_write(ring, 0x68e04); in jpeg_v2_0_dec_ring_insert_end()
483 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in jpeg_v2_0_dec_ring_insert_end()
485 amdgpu_ring_write(ring, 0x00010000); in jpeg_v2_0_dec_ring_insert_end()
491 * @ring: amdgpu_ring pointer
494 * Write a fence and a trap command to the ring.
496 void jpeg_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, in jpeg_v2_0_dec_ring_emit_fence() argument
501 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_fence()
503 amdgpu_ring_write(ring, seq); in jpeg_v2_0_dec_ring_emit_fence()
505 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_fence()
507 amdgpu_ring_write(ring, seq); in jpeg_v2_0_dec_ring_emit_fence()
509 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_fence()
511 amdgpu_ring_write(ring, lower_32_bits(addr)); in jpeg_v2_0_dec_ring_emit_fence()
513 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_fence()
515 amdgpu_ring_write(ring, upper_32_bits(addr)); in jpeg_v2_0_dec_ring_emit_fence()
517 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_fence()
519 amdgpu_ring_write(ring, 0x8); in jpeg_v2_0_dec_ring_emit_fence()
521 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_fence()
523 amdgpu_ring_write(ring, 0); in jpeg_v2_0_dec_ring_emit_fence()
525 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_fence()
527 amdgpu_ring_write(ring, 0x3fbc); in jpeg_v2_0_dec_ring_emit_fence()
529 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in jpeg_v2_0_dec_ring_emit_fence()
531 amdgpu_ring_write(ring, 0x1); in jpeg_v2_0_dec_ring_emit_fence()
533 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7)); in jpeg_v2_0_dec_ring_emit_fence()
534 amdgpu_ring_write(ring, 0); in jpeg_v2_0_dec_ring_emit_fence()
540 * @ring: amdgpu_ring pointer
543 * Write ring commands to execute the indirect buffer.
545 void jpeg_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring, in jpeg_v2_0_dec_ring_emit_ib() argument
552 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_ib()
554 amdgpu_ring_write(ring, (vmid | (vmid << 4))); in jpeg_v2_0_dec_ring_emit_ib()
556 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_ib()
558 amdgpu_ring_write(ring, (vmid | (vmid << 4))); in jpeg_v2_0_dec_ring_emit_ib()
560 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_ib()
562 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in jpeg_v2_0_dec_ring_emit_ib()
564 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_ib()
566 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in jpeg_v2_0_dec_ring_emit_ib()
568 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_ib()
570 amdgpu_ring_write(ring, ib->length_dw); in jpeg_v2_0_dec_ring_emit_ib()
572 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_ib()
574 amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr)); in jpeg_v2_0_dec_ring_emit_ib()
576 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_ib()
578 amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr)); in jpeg_v2_0_dec_ring_emit_ib()
580 amdgpu_ring_write(ring, PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2)); in jpeg_v2_0_dec_ring_emit_ib()
581 amdgpu_ring_write(ring, 0); in jpeg_v2_0_dec_ring_emit_ib()
583 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_ib()
585 amdgpu_ring_write(ring, 0x01400200); in jpeg_v2_0_dec_ring_emit_ib()
587 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_ib()
589 amdgpu_ring_write(ring, 0x2); in jpeg_v2_0_dec_ring_emit_ib()
591 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_STATUS_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_ib()
593 amdgpu_ring_write(ring, 0x2); in jpeg_v2_0_dec_ring_emit_ib()
596 void jpeg_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, in jpeg_v2_0_dec_ring_emit_reg_wait() argument
601 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_reg_wait()
603 amdgpu_ring_write(ring, 0x01400200); in jpeg_v2_0_dec_ring_emit_reg_wait()
605 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_reg_wait()
607 amdgpu_ring_write(ring, val); in jpeg_v2_0_dec_ring_emit_reg_wait()
609 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_reg_wait()
612 amdgpu_ring_write(ring, 0); in jpeg_v2_0_dec_ring_emit_reg_wait()
613 amdgpu_ring_write(ring, in jpeg_v2_0_dec_ring_emit_reg_wait()
616 amdgpu_ring_write(ring, reg_offset); in jpeg_v2_0_dec_ring_emit_reg_wait()
617 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in jpeg_v2_0_dec_ring_emit_reg_wait()
620 amdgpu_ring_write(ring, mask); in jpeg_v2_0_dec_ring_emit_reg_wait()
623 void jpeg_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, in jpeg_v2_0_dec_ring_emit_vm_flush() argument
626 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; in jpeg_v2_0_dec_ring_emit_vm_flush()
629 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); in jpeg_v2_0_dec_ring_emit_vm_flush()
635 jpeg_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask); in jpeg_v2_0_dec_ring_emit_vm_flush()
638 void jpeg_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) in jpeg_v2_0_dec_ring_emit_wreg() argument
642 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_wreg()
645 amdgpu_ring_write(ring, 0); in jpeg_v2_0_dec_ring_emit_wreg()
646 amdgpu_ring_write(ring, in jpeg_v2_0_dec_ring_emit_wreg()
649 amdgpu_ring_write(ring, reg_offset); in jpeg_v2_0_dec_ring_emit_wreg()
650 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in jpeg_v2_0_dec_ring_emit_wreg()
653 amdgpu_ring_write(ring, val); in jpeg_v2_0_dec_ring_emit_wreg()
656 void jpeg_v2_0_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count) in jpeg_v2_0_dec_ring_nop() argument
660 WARN_ON(ring->wptr % 2 || count % 2); in jpeg_v2_0_dec_ring_nop()
663 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); in jpeg_v2_0_dec_ring_nop()
664 amdgpu_ring_write(ring, 0); in jpeg_v2_0_dec_ring_nop()