Lines Matching +full:0 +full:x00001000
64 …HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d
66 …DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0
67 …CSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10
68 …RI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL
69 …RI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L
70 …DCHUBBUB_SDPIF_MMIO_CNTRL_0 0x049d
91 [0][0] = "MP1",
92 [1][0] = "MP0",
93 [2][0] = "VCN",
94 [3][0] = "VCNU",
95 [4][0] = "HDP",
96 [5][0] = "DCE",
97 [13][0] = "UTCL2",
98 [19][0] = "TLS",
99 [26][0] = "OSS",
100 [27][0] = "SDMA0",
101 [0][1] = "MP1",
116 [0][0] = "MP1",
117 [1][0] = "MP0",
118 [2][0] = "HDP",
119 [4][0] = "DCEDMC",
120 [5][0] = "DCEVGA",
121 [13][0] = "UTCL2",
122 [19][0] = "TLS",
123 [26][0] = "OSS",
124 [27][0] = "SDMA0",
125 [28][0] = "VCN",
126 [29][0] = "VCNU",
127 [30][0] = "JPEG",
128 [0][1] = "MP1",
144 [0][0] = "MP0",
145 [1][0] = "UVD",
146 [2][0] = "UVDU",
147 [3][0] = "HDP",
148 [13][0] = "UTCL2",
149 [14][0] = "OSS",
150 [15][0] = "SDMA1",
151 [32+0][0] = "VCE0",
152 [32+1][0] = "VCE0U",
153 [32+2][0] = "XDMA",
154 [32+3][0] = "DCE",
155 [32+4][0] = "MP1",
156 [32+14][0] = "SDMA0",
157 [0][1] = "MP0",
165 [32+0][1] = "VCE0",
176 [0][0] = "MP0",
177 [1][0] = "VCE0",
178 [2][0] = "VCE0U",
179 [3][0] = "HDP",
180 [13][0] = "UTCL2",
181 [14][0] = "OSS",
182 [15][0] = "SDMA1",
183 [32+0][0] = "DCE",
184 [32+1][0] = "XDMA",
185 [32+2][0] = "UVD",
186 [32+3][0] = "UVDU",
187 [32+4][0] = "MP1",
188 [32+15][0] = "SDMA0",
189 [0][1] = "MP0",
197 [32+0][1] = "DCE",
208 [0][0] = "XDMA",
209 [1][0] = "DCE",
210 [2][0] = "VCE0",
211 [3][0] = "VCE0U",
212 [4][0] = "UVD",
213 [5][0] = "UVD1U",
214 [13][0] = "OSS",
215 [14][0] = "HDP",
216 [15][0] = "SDMA0",
217 [32+0][0] = "UVD",
218 [32+1][0] = "UVDU",
219 [32+2][0] = "MP1",
220 [32+3][0] = "MP0",
221 [32+12][0] = "UTCL2",
222 [32+14][0] = "SDMA1",
223 [0][1] = "XDMA",
235 [32+0][1] = "UVD",
244 [2][0] = "MP1",
245 [3][0] = "MP0",
246 [10][0] = "UTCL2",
247 [13][0] = "OSS",
248 [14][0] = "HDP",
249 [15][0] = "SDMA0",
250 [32+15][0] = "SDMA1",
251 [64+15][0] = "SDMA2",
252 [96+15][0] = "SDMA3",
253 [128+15][0] = "SDMA4",
254 [160+11][0] = "JPEG",
255 [160+12][0] = "VCN",
256 [160+13][0] = "VCNU",
257 [160+15][0] = "SDMA5",
258 [192+10][0] = "UTCL2",
259 [192+11][0] = "JPEG1",
260 [192+12][0] = "VCN1",
261 [192+13][0] = "VCN1U",
262 [192+15][0] = "SDMA6",
263 [224+15][0] = "SDMA7",
264 [0][1] = "DBGU1",
288 0xf64, 0x0fffffff, 0x00000000,
289 0xf65, 0x0fffffff, 0x00000000,
290 0xf66, 0x0fffffff, 0x00000000,
291 0xf67, 0x0fffffff, 0x00000000,
292 0xf68, 0x0fffffff, 0x00000000,
293 0xf6a, 0x0fffffff, 0x00000000,
294 0xf6b, 0x0fffffff, 0x00000000,
295 0xf6c, 0x0fffffff, 0x00000000,
296 0xf6d, 0x0fffffff, 0x00000000,
297 0xf6e, 0x0fffffff, 0x00000000,
302 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa),
303 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565)
308 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800),
309 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008)
313 (0x000143c0 + 0x00000000),
314 (0x000143c0 + 0x00000800),
315 (0x000143c0 + 0x00001000),
316 (0x000143c0 + 0x00001800),
317 (0x000543c0 + 0x00000000),
318 (0x000543c0 + 0x00000800),
319 (0x000543c0 + 0x00001000),
320 (0x000543c0 + 0x00001800),
321 (0x000943c0 + 0x00000000),
322 (0x000943c0 + 0x00000800),
323 (0x000943c0 + 0x00001000),
324 (0x000943c0 + 0x00001800),
325 (0x000d43c0 + 0x00000000),
326 (0x000d43c0 + 0x00000800),
327 (0x000d43c0 + 0x00001000),
328 (0x000d43c0 + 0x00001800),
329 (0x001143c0 + 0x00000000),
330 (0x001143c0 + 0x00000800),
331 (0x001143c0 + 0x00001000),
332 (0x001143c0 + 0x00001800),
333 (0x001543c0 + 0x00000000),
334 (0x001543c0 + 0x00000800),
335 (0x001543c0 + 0x00001000),
336 (0x001543c0 + 0x00001800),
337 (0x001943c0 + 0x00000000),
338 (0x001943c0 + 0x00000800),
339 (0x001943c0 + 0x00001000),
340 (0x001943c0 + 0x00001800),
341 (0x001d43c0 + 0x00000000),
342 (0x001d43c0 + 0x00000800),
343 (0x001d43c0 + 0x00001000),
344 (0x001d43c0 + 0x00001800),
348 (0x000143e0 + 0x00000000),
349 (0x000143e0 + 0x00000800),
350 (0x000143e0 + 0x00001000),
351 (0x000143e0 + 0x00001800),
352 (0x000543e0 + 0x00000000),
353 (0x000543e0 + 0x00000800),
354 (0x000543e0 + 0x00001000),
355 (0x000543e0 + 0x00001800),
356 (0x000943e0 + 0x00000000),
357 (0x000943e0 + 0x00000800),
358 (0x000943e0 + 0x00001000),
359 (0x000943e0 + 0x00001800),
360 (0x000d43e0 + 0x00000000),
361 (0x000d43e0 + 0x00000800),
362 (0x000d43e0 + 0x00001000),
363 (0x000d43e0 + 0x00001800),
364 (0x001143e0 + 0x00000000),
365 (0x001143e0 + 0x00000800),
366 (0x001143e0 + 0x00001000),
367 (0x001143e0 + 0x00001800),
368 (0x001543e0 + 0x00000000),
369 (0x001543e0 + 0x00000800),
370 (0x001543e0 + 0x00001000),
371 (0x001543e0 + 0x00001800),
372 (0x001943e0 + 0x00000000),
373 (0x001943e0 + 0x00000800),
374 (0x001943e0 + 0x00001000),
375 (0x001943e0 + 0x00001800),
376 (0x001d43e0 + 0x00000000),
377 (0x001d43e0 + 0x00000800),
378 (0x001d43e0 + 0x00001000),
379 (0x001d43e0 + 0x00001800),
383 (0x000143c2 + 0x00000000),
384 (0x000143c2 + 0x00000800),
385 (0x000143c2 + 0x00001000),
386 (0x000143c2 + 0x00001800),
387 (0x000543c2 + 0x00000000),
388 (0x000543c2 + 0x00000800),
389 (0x000543c2 + 0x00001000),
390 (0x000543c2 + 0x00001800),
391 (0x000943c2 + 0x00000000),
392 (0x000943c2 + 0x00000800),
393 (0x000943c2 + 0x00001000),
394 (0x000943c2 + 0x00001800),
395 (0x000d43c2 + 0x00000000),
396 (0x000d43c2 + 0x00000800),
397 (0x000d43c2 + 0x00001000),
398 (0x000d43c2 + 0x00001800),
399 (0x001143c2 + 0x00000000),
400 (0x001143c2 + 0x00000800),
401 (0x001143c2 + 0x00001000),
402 (0x001143c2 + 0x00001800),
403 (0x001543c2 + 0x00000000),
404 (0x001543c2 + 0x00000800),
405 (0x001543c2 + 0x00001000),
406 (0x001543c2 + 0x00001800),
407 (0x001943c2 + 0x00000000),
408 (0x001943c2 + 0x00000800),
409 (0x001943c2 + 0x00001000),
410 (0x001943c2 + 0x00001800),
411 (0x001d43c2 + 0x00000000),
412 (0x001d43c2 + 0x00000800),
413 (0x001d43c2 + 0x00001000),
414 (0x001d43c2 + 0x00001800),
427 return 0; in gmc_v9_0_ecc_interrupt_state()
429 bits = 0x7f; in gmc_v9_0_ecc_interrupt_state()
433 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { in gmc_v9_0_ecc_interrupt_state()
439 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { in gmc_v9_0_ecc_interrupt_state()
447 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { in gmc_v9_0_ecc_interrupt_state()
453 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { in gmc_v9_0_ecc_interrupt_state()
464 return 0; in gmc_v9_0_ecc_interrupt_state()
485 for (j = 0; j < adev->num_vmhubs; j++) { in gmc_v9_0_vm_fault_interrupt_state()
487 for (i = 0; i < 16; i++) { in gmc_v9_0_vm_fault_interrupt_state()
496 for (j = 0; j < adev->num_vmhubs; j++) { in gmc_v9_0_vm_fault_interrupt_state()
498 for (i = 0; i < 16; i++) { in gmc_v9_0_vm_fault_interrupt_state()
509 return 0; in gmc_v9_0_vm_fault_interrupt_state()
517 bool retry_fault = !!(entry->src_data[1] & 0x80); in gmc_v9_0_process_interrupt()
518 uint32_t status = 0, cid = 0, rw = 0; in gmc_v9_0_process_interrupt()
523 addr = (u64)entry->src_data[0] << 12; in gmc_v9_0_process_interrupt()
524 addr |= ((u64)entry->src_data[1] & 0xf) << 44; in gmc_v9_0_process_interrupt()
566 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); in gmc_v9_0_process_interrupt()
576 dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n", in gmc_v9_0_process_interrupt()
580 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", in gmc_v9_0_process_interrupt()
583 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", in gmc_v9_0_process_interrupt()
610 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", in gmc_v9_0_process_interrupt()
613 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", in gmc_v9_0_process_interrupt()
616 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", in gmc_v9_0_process_interrupt()
619 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", in gmc_v9_0_process_interrupt()
622 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", in gmc_v9_0_process_interrupt()
625 dev_err(adev->dev, "\t RW: 0x%x\n", rw); in gmc_v9_0_process_interrupt()
629 return 0; in gmc_v9_0_process_interrupt()
657 u32 req = 0; in gmc_v9_0_get_invalidate_req()
668 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); in gmc_v9_0_get_invalidate_req()
695 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) in gmc_v9_0_get_atc_vmid_pasid_mapping_info()
704 * VMID 0 is the physical GPU addresses as used by the kernel.
741 inv_req2 = 0; in gmc_v9_0_flush_gpu_tlb()
770 for (j = 0; j < adev->usec_timeout; j++) { in gmc_v9_0_flush_gpu_tlb()
774 if (tmp & 0x1) in gmc_v9_0_flush_gpu_tlb()
796 for (j = 0; j < adev->usec_timeout; j++) { in gmc_v9_0_flush_gpu_tlb()
805 inv_req2 = 0; in gmc_v9_0_flush_gpu_tlb()
812 * write with 0 means semaphore release in gmc_v9_0_flush_gpu_tlb()
815 hub->eng_distance * eng, 0); in gmc_v9_0_flush_gpu_tlb()
888 return 0; in gmc_v9_0_flush_gpu_tlb_pasid()
897 for (i = 0; i < adev->num_vmhubs; i++) in gmc_v9_0_flush_gpu_tlb_pasid()
908 return 0; in gmc_v9_0_flush_gpu_tlb_pasid()
918 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); in gmc_v9_0_emit_flush_gpu_tlb()
933 hub->eng_distance * eng, 0x1, 0x1); in gmc_v9_0_emit_flush_gpu_tlb()
953 * write with 0 means semaphore release in gmc_v9_0_emit_flush_gpu_tlb()
956 hub->eng_distance * eng, 0); in gmc_v9_0_emit_flush_gpu_tlb()
972 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; in gmc_v9_0_emit_pasid_mapping()
974 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; in gmc_v9_0_emit_pasid_mapping()
997 * 0 valid
1008 * 0 valid
1038 BUG_ON(*addr & 0xFFFF00000000003FULL); in gmc_v9_0_get_vm_pde()
1046 *flags |= AMDGPU_PDE_BFS(0x9); in gmc_v9_0_get_vm_pde()
1079 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); in gmc_v9_0_get_vbios_fb_size()
1090 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); in gmc_v9_0_get_vbios_fb_size()
1101 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE); in gmc_v9_0_get_vbios_fb_size()
1139 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; in gmc_v9_0_set_umc_funcs()
1147 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; in gmc_v9_0_set_umc_funcs()
1190 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; in gmc_v9_0_early_init()
1193 adev->gmc.private_aperture_start = 0x1000000000000000ULL; in gmc_v9_0_early_init()
1197 return 0; in gmc_v9_0_early_init()
1229 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); in gmc_v9_0_late_init()
1235 u64 base = 0; in gmc_v9_0_vram_gtt_location()
1260 * Returns 0 for success.
1276 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); in gmc_v9_0_mc_init()
1277 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); in gmc_v9_0_mc_init()
1311 return 0; in gmc_v9_0_mc_init()
1320 return 0; in gmc_v9_0_gart_init()
1343 adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0); in gmc_v9_0_save_registers()
1348 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; in gmc_v9_0_sw_init()
1387 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { in gmc_v9_0_sw_init()
1445 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, in gmc_v9_0_sw_init()
1455 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ in gmc_v9_0_sw_init()
1487 * VMID 0 is reserved for System in gmc_v9_0_sw_init()
1502 return 0; in gmc_v9_0_sw_init()
1516 return 0; in gmc_v9_0_sw_fini()
1558 WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register); in gmc_v9_0_restore_registers()
1560 RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0)); in gmc_v9_0_restore_registers()
1589 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", in gmc_v9_0_gart_enable()
1593 return 0; in gmc_v9_0_gart_enable()
1609 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); in gmc_v9_0_hw_init()
1612 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); in gmc_v9_0_hw_init()
1625 WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1); in gmc_v9_0_hw_init()
1631 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1); in gmc_v9_0_hw_init()
1633 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL); in gmc_v9_0_hw_init()
1634 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp); in gmc_v9_0_hw_init()
1636 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); in gmc_v9_0_hw_init()
1637 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40)); in gmc_v9_0_hw_init()
1651 for (i = 0; i < adev->num_vmhubs; ++i) in gmc_v9_0_hw_init()
1652 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0); in gmc_v9_0_hw_init()
1683 return 0; in gmc_v9_0_hw_fini()
1686 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); in gmc_v9_0_hw_fini()
1687 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); in gmc_v9_0_hw_fini()
1690 return 0; in gmc_v9_0_hw_fini()
1711 return 0; in gmc_v9_0_resume()
1723 return 0; in gmc_v9_0_wait_for_idle()
1729 return 0; in gmc_v9_0_soft_reset()
1741 return 0; in gmc_v9_0_set_clockgating_state()
1756 return 0; in gmc_v9_0_set_powergating_state()
1781 .minor = 0,
1782 .rev = 0,