Lines Matching refs:tmp
199 u32 tmp; in gmc_v8_0_mc_resume() local
202 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v8_0_mc_resume()
203 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); in gmc_v8_0_mc_resume()
204 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); in gmc_v8_0_mc_resume()
206 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); in gmc_v8_0_mc_resume()
207 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); in gmc_v8_0_mc_resume()
208 WREG32(mmBIF_FB_EN, tmp); in gmc_v8_0_mc_resume()
453 u32 tmp; in gmc_v8_0_mc_program() local
471 tmp = RREG32(mmVGA_HDP_CONTROL); in gmc_v8_0_mc_program()
472 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); in gmc_v8_0_mc_program()
473 WREG32(mmVGA_HDP_CONTROL, tmp); in gmc_v8_0_mc_program()
476 tmp = RREG32(mmVGA_RENDER_CONTROL); in gmc_v8_0_mc_program()
477 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); in gmc_v8_0_mc_program()
478 WREG32(mmVGA_RENDER_CONTROL, tmp); in gmc_v8_0_mc_program()
489 tmp = ((adev->gmc.vram_end >> 24) & 0xFFFF) << 16; in gmc_v8_0_mc_program()
490 tmp |= ((adev->gmc.vram_start >> 24) & 0xFFFF); in gmc_v8_0_mc_program()
491 WREG32(mmMC_VM_FB_LOCATION, tmp); in gmc_v8_0_mc_program()
507 tmp = RREG32(mmHDP_MISC_CNTL); in gmc_v8_0_mc_program()
508 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0); in gmc_v8_0_mc_program()
509 WREG32(mmHDP_MISC_CNTL, tmp); in gmc_v8_0_mc_program()
511 tmp = RREG32(mmHDP_HOST_PATH_CNTL); in gmc_v8_0_mc_program()
512 WREG32(mmHDP_HOST_PATH_CNTL, tmp); in gmc_v8_0_mc_program()
530 u32 tmp; in gmc_v8_0_mc_init() local
534 tmp = RREG32(mmMC_ARB_RAMCFG); in gmc_v8_0_mc_init()
535 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { in gmc_v8_0_mc_init()
540 tmp = RREG32(mmMC_SHARED_CHMAP); in gmc_v8_0_mc_init()
541 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { in gmc_v8_0_mc_init()
636 unsigned int tmp; in gmc_v8_0_flush_gpu_tlb_pasid() local
643 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); in gmc_v8_0_flush_gpu_tlb_pasid()
644 if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) && in gmc_v8_0_flush_gpu_tlb_pasid()
645 (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) { in gmc_v8_0_flush_gpu_tlb_pasid()
746 u32 tmp; in gmc_v8_0_set_fault_enable_default() local
748 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v8_0_set_fault_enable_default()
749 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v8_0_set_fault_enable_default()
751 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v8_0_set_fault_enable_default()
753 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v8_0_set_fault_enable_default()
755 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v8_0_set_fault_enable_default()
757 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v8_0_set_fault_enable_default()
759 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v8_0_set_fault_enable_default()
761 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v8_0_set_fault_enable_default()
763 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v8_0_set_fault_enable_default()
774 u32 tmp; in gmc_v8_0_set_prt() local
781 tmp = RREG32(mmVM_PRT_CNTL); in gmc_v8_0_set_prt()
782 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, in gmc_v8_0_set_prt()
784 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, in gmc_v8_0_set_prt()
786 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, in gmc_v8_0_set_prt()
788 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, in gmc_v8_0_set_prt()
790 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, in gmc_v8_0_set_prt()
792 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, in gmc_v8_0_set_prt()
794 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, in gmc_v8_0_set_prt()
796 WREG32(mmVM_PRT_CNTL, tmp); in gmc_v8_0_set_prt()
838 u32 tmp, field; in gmc_v8_0_gart_enable() local
851 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); in gmc_v8_0_gart_enable()
852 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gmc_v8_0_gart_enable()
853 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1); in gmc_v8_0_gart_enable()
854 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in gmc_v8_0_gart_enable()
855 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1); in gmc_v8_0_gart_enable()
856 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); in gmc_v8_0_gart_enable()
857 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); in gmc_v8_0_gart_enable()
859 tmp = RREG32(mmVM_L2_CNTL); in gmc_v8_0_gart_enable()
860 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in gmc_v8_0_gart_enable()
861 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); in gmc_v8_0_gart_enable()
862 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v8_0_gart_enable()
863 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v8_0_gart_enable()
864 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); in gmc_v8_0_gart_enable()
865 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); in gmc_v8_0_gart_enable()
866 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); in gmc_v8_0_gart_enable()
867 WREG32(mmVM_L2_CNTL, tmp); in gmc_v8_0_gart_enable()
868 tmp = RREG32(mmVM_L2_CNTL2); in gmc_v8_0_gart_enable()
869 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gmc_v8_0_gart_enable()
870 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gmc_v8_0_gart_enable()
871 WREG32(mmVM_L2_CNTL2, tmp); in gmc_v8_0_gart_enable()
874 tmp = RREG32(mmVM_L2_CNTL3); in gmc_v8_0_gart_enable()
875 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); in gmc_v8_0_gart_enable()
876 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); in gmc_v8_0_gart_enable()
877 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field); in gmc_v8_0_gart_enable()
878 WREG32(mmVM_L2_CNTL3, tmp); in gmc_v8_0_gart_enable()
880 tmp = RREG32(mmVM_L2_CNTL4); in gmc_v8_0_gart_enable()
881 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0); in gmc_v8_0_gart_enable()
882 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0); in gmc_v8_0_gart_enable()
883 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0); in gmc_v8_0_gart_enable()
884 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0); in gmc_v8_0_gart_enable()
885 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0); in gmc_v8_0_gart_enable()
886 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0); in gmc_v8_0_gart_enable()
887 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0); in gmc_v8_0_gart_enable()
888 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0); in gmc_v8_0_gart_enable()
889 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0); in gmc_v8_0_gart_enable()
890 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0); in gmc_v8_0_gart_enable()
891 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0); in gmc_v8_0_gart_enable()
892 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0); in gmc_v8_0_gart_enable()
893 WREG32(mmVM_L2_CNTL4, tmp); in gmc_v8_0_gart_enable()
901 tmp = RREG32(mmVM_CONTEXT0_CNTL); in gmc_v8_0_gart_enable()
902 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in gmc_v8_0_gart_enable()
903 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); in gmc_v8_0_gart_enable()
904 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); in gmc_v8_0_gart_enable()
905 WREG32(mmVM_CONTEXT0_CNTL, tmp); in gmc_v8_0_gart_enable()
931 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v8_0_gart_enable()
932 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in gmc_v8_0_gart_enable()
933 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); in gmc_v8_0_gart_enable()
934 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); in gmc_v8_0_gart_enable()
935 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); in gmc_v8_0_gart_enable()
936 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); in gmc_v8_0_gart_enable()
937 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); in gmc_v8_0_gart_enable()
938 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); in gmc_v8_0_gart_enable()
939 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); in gmc_v8_0_gart_enable()
940 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); in gmc_v8_0_gart_enable()
941 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, in gmc_v8_0_gart_enable()
943 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v8_0_gart_enable()
983 u32 tmp; in gmc_v8_0_gart_disable() local
989 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); in gmc_v8_0_gart_disable()
990 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gmc_v8_0_gart_disable()
991 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0); in gmc_v8_0_gart_disable()
992 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0); in gmc_v8_0_gart_disable()
993 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); in gmc_v8_0_gart_disable()
995 tmp = RREG32(mmVM_L2_CNTL); in gmc_v8_0_gart_disable()
996 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); in gmc_v8_0_gart_disable()
997 WREG32(mmVM_L2_CNTL, tmp); in gmc_v8_0_gart_disable()
1113 u32 tmp; in gmc_v8_0_sw_init() local
1117 tmp = RREG32(mmMC_SEQ_MISC0_FIJI); in gmc_v8_0_sw_init()
1119 tmp = RREG32(mmMC_SEQ_MISC0); in gmc_v8_0_sw_init()
1120 tmp &= MC_SEQ_MISC0__MT__MASK; in gmc_v8_0_sw_init()
1121 adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp); in gmc_v8_0_sw_init()
1183 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); in gmc_v8_0_sw_init() local
1185 tmp <<= 22; in gmc_v8_0_sw_init()
1186 adev->vm_manager.vram_base_offset = tmp; in gmc_v8_0_sw_init()
1284 u32 tmp = RREG32(mmSRBM_STATUS); in gmc_v8_0_is_idle() local
1286 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | in gmc_v8_0_is_idle()
1296 u32 tmp; in gmc_v8_0_wait_for_idle() local
1301 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | in gmc_v8_0_wait_for_idle()
1307 if (!tmp) in gmc_v8_0_wait_for_idle()
1319 u32 tmp = RREG32(mmSRBM_STATUS); in gmc_v8_0_check_soft_reset() local
1321 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) in gmc_v8_0_check_soft_reset()
1325 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | in gmc_v8_0_check_soft_reset()
1365 u32 tmp; in gmc_v8_0_soft_reset() local
1367 tmp = RREG32(mmSRBM_SOFT_RESET); in gmc_v8_0_soft_reset()
1368 tmp |= srbm_soft_reset; in gmc_v8_0_soft_reset()
1369 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in gmc_v8_0_soft_reset()
1370 WREG32(mmSRBM_SOFT_RESET, tmp); in gmc_v8_0_soft_reset()
1371 tmp = RREG32(mmSRBM_SOFT_RESET); in gmc_v8_0_soft_reset()
1375 tmp &= ~srbm_soft_reset; in gmc_v8_0_soft_reset()
1376 WREG32(mmSRBM_SOFT_RESET, tmp); in gmc_v8_0_soft_reset()
1377 tmp = RREG32(mmSRBM_SOFT_RESET); in gmc_v8_0_soft_reset()
1402 u32 tmp; in gmc_v8_0_vm_fault_interrupt_state() local
1414 tmp = RREG32(mmVM_CONTEXT0_CNTL); in gmc_v8_0_vm_fault_interrupt_state()
1415 tmp &= ~bits; in gmc_v8_0_vm_fault_interrupt_state()
1416 WREG32(mmVM_CONTEXT0_CNTL, tmp); in gmc_v8_0_vm_fault_interrupt_state()
1418 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v8_0_vm_fault_interrupt_state()
1419 tmp &= ~bits; in gmc_v8_0_vm_fault_interrupt_state()
1420 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v8_0_vm_fault_interrupt_state()
1424 tmp = RREG32(mmVM_CONTEXT0_CNTL); in gmc_v8_0_vm_fault_interrupt_state()
1425 tmp |= bits; in gmc_v8_0_vm_fault_interrupt_state()
1426 WREG32(mmVM_CONTEXT0_CNTL, tmp); in gmc_v8_0_vm_fault_interrupt_state()
1428 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v8_0_vm_fault_interrupt_state()
1429 tmp |= bits; in gmc_v8_0_vm_fault_interrupt_state()
1430 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v8_0_vm_fault_interrupt_state()