Lines Matching refs:tmp
111 u32 tmp; in gmc_v7_0_mc_resume() local
114 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v7_0_mc_resume()
115 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); in gmc_v7_0_mc_resume()
116 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); in gmc_v7_0_mc_resume()
118 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); in gmc_v7_0_mc_resume()
119 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); in gmc_v7_0_mc_resume()
120 WREG32(mmBIF_FB_EN, tmp); in gmc_v7_0_mc_resume()
262 u32 tmp; in gmc_v7_0_mc_program() local
280 tmp = RREG32(mmVGA_HDP_CONTROL); in gmc_v7_0_mc_program()
281 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); in gmc_v7_0_mc_program()
282 WREG32(mmVGA_HDP_CONTROL, tmp); in gmc_v7_0_mc_program()
285 tmp = RREG32(mmVGA_RENDER_CONTROL); in gmc_v7_0_mc_program()
286 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); in gmc_v7_0_mc_program()
287 WREG32(mmVGA_RENDER_CONTROL, tmp); in gmc_v7_0_mc_program()
305 tmp = RREG32(mmHDP_MISC_CNTL); in gmc_v7_0_mc_program()
306 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0); in gmc_v7_0_mc_program()
307 WREG32(mmHDP_MISC_CNTL, tmp); in gmc_v7_0_mc_program()
309 tmp = RREG32(mmHDP_HOST_PATH_CNTL); in gmc_v7_0_mc_program()
310 WREG32(mmHDP_HOST_PATH_CNTL, tmp); in gmc_v7_0_mc_program()
328 u32 tmp; in gmc_v7_0_mc_init() local
332 tmp = RREG32(mmMC_ARB_RAMCFG); in gmc_v7_0_mc_init()
333 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { in gmc_v7_0_mc_init()
338 tmp = RREG32(mmMC_SHARED_CHMAP); in gmc_v7_0_mc_init()
339 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { in gmc_v7_0_mc_init()
435 unsigned int tmp; in gmc_v7_0_flush_gpu_tlb_pasid() local
442 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); in gmc_v7_0_flush_gpu_tlb_pasid()
443 if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) && in gmc_v7_0_flush_gpu_tlb_pasid()
444 (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) { in gmc_v7_0_flush_gpu_tlb_pasid()
522 u32 tmp; in gmc_v7_0_set_fault_enable_default() local
524 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v7_0_set_fault_enable_default()
525 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v7_0_set_fault_enable_default()
527 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v7_0_set_fault_enable_default()
529 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v7_0_set_fault_enable_default()
531 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v7_0_set_fault_enable_default()
533 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v7_0_set_fault_enable_default()
535 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v7_0_set_fault_enable_default()
537 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v7_0_set_fault_enable_default()
548 uint32_t tmp; in gmc_v7_0_set_prt() local
555 tmp = RREG32(mmVM_PRT_CNTL); in gmc_v7_0_set_prt()
556 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, in gmc_v7_0_set_prt()
558 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, in gmc_v7_0_set_prt()
560 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, in gmc_v7_0_set_prt()
562 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, in gmc_v7_0_set_prt()
564 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, in gmc_v7_0_set_prt()
566 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, in gmc_v7_0_set_prt()
568 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, in gmc_v7_0_set_prt()
570 WREG32(mmVM_PRT_CNTL, tmp); in gmc_v7_0_set_prt()
612 u32 tmp, field; in gmc_v7_0_gart_enable() local
625 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); in gmc_v7_0_gart_enable()
626 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gmc_v7_0_gart_enable()
627 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1); in gmc_v7_0_gart_enable()
628 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in gmc_v7_0_gart_enable()
629 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1); in gmc_v7_0_gart_enable()
630 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); in gmc_v7_0_gart_enable()
631 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); in gmc_v7_0_gart_enable()
633 tmp = RREG32(mmVM_L2_CNTL); in gmc_v7_0_gart_enable()
634 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in gmc_v7_0_gart_enable()
635 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); in gmc_v7_0_gart_enable()
636 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v7_0_gart_enable()
637 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v7_0_gart_enable()
638 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); in gmc_v7_0_gart_enable()
639 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); in gmc_v7_0_gart_enable()
640 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); in gmc_v7_0_gart_enable()
641 WREG32(mmVM_L2_CNTL, tmp); in gmc_v7_0_gart_enable()
642 tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gmc_v7_0_gart_enable()
643 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gmc_v7_0_gart_enable()
644 WREG32(mmVM_L2_CNTL2, tmp); in gmc_v7_0_gart_enable()
647 tmp = RREG32(mmVM_L2_CNTL3); in gmc_v7_0_gart_enable()
648 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); in gmc_v7_0_gart_enable()
649 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); in gmc_v7_0_gart_enable()
650 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field); in gmc_v7_0_gart_enable()
651 WREG32(mmVM_L2_CNTL3, tmp); in gmc_v7_0_gart_enable()
659 tmp = RREG32(mmVM_CONTEXT0_CNTL); in gmc_v7_0_gart_enable()
660 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in gmc_v7_0_gart_enable()
661 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); in gmc_v7_0_gart_enable()
662 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); in gmc_v7_0_gart_enable()
663 WREG32(mmVM_CONTEXT0_CNTL, tmp); in gmc_v7_0_gart_enable()
689 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v7_0_gart_enable()
690 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in gmc_v7_0_gart_enable()
691 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); in gmc_v7_0_gart_enable()
692 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, in gmc_v7_0_gart_enable()
694 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v7_0_gart_enable()
701 tmp = RREG32(mmCHUB_CONTROL); in gmc_v7_0_gart_enable()
702 tmp &= ~BYPASS_VM; in gmc_v7_0_gart_enable()
703 WREG32(mmCHUB_CONTROL, tmp); in gmc_v7_0_gart_enable()
740 u32 tmp; in gmc_v7_0_gart_disable() local
746 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); in gmc_v7_0_gart_disable()
747 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gmc_v7_0_gart_disable()
748 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0); in gmc_v7_0_gart_disable()
749 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0); in gmc_v7_0_gart_disable()
750 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); in gmc_v7_0_gart_disable()
752 tmp = RREG32(mmVM_L2_CNTL); in gmc_v7_0_gart_disable()
753 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); in gmc_v7_0_gart_disable()
754 WREG32(mmVM_L2_CNTL, tmp); in gmc_v7_0_gart_disable()
994 u32 tmp = RREG32(mmMC_SEQ_MISC0); in gmc_v7_0_sw_init() local
995 tmp &= MC_SEQ_MISC0__MT__MASK; in gmc_v7_0_sw_init()
996 adev->gmc.vram_type = gmc_v7_0_convert_vram_type(tmp); in gmc_v7_0_sw_init()
1058 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); in gmc_v7_0_sw_init() local
1060 tmp <<= 22; in gmc_v7_0_sw_init()
1061 adev->vm_manager.vram_base_offset = tmp; in gmc_v7_0_sw_init()
1151 u32 tmp = RREG32(mmSRBM_STATUS); in gmc_v7_0_is_idle() local
1153 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | in gmc_v7_0_is_idle()
1163 u32 tmp; in gmc_v7_0_wait_for_idle() local
1168 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | in gmc_v7_0_wait_for_idle()
1173 if (!tmp) in gmc_v7_0_wait_for_idle()
1185 u32 tmp = RREG32(mmSRBM_STATUS); in gmc_v7_0_soft_reset() local
1187 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) in gmc_v7_0_soft_reset()
1191 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | in gmc_v7_0_soft_reset()
1205 tmp = RREG32(mmSRBM_SOFT_RESET); in gmc_v7_0_soft_reset()
1206 tmp |= srbm_soft_reset; in gmc_v7_0_soft_reset()
1207 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in gmc_v7_0_soft_reset()
1208 WREG32(mmSRBM_SOFT_RESET, tmp); in gmc_v7_0_soft_reset()
1209 tmp = RREG32(mmSRBM_SOFT_RESET); in gmc_v7_0_soft_reset()
1213 tmp &= ~srbm_soft_reset; in gmc_v7_0_soft_reset()
1214 WREG32(mmSRBM_SOFT_RESET, tmp); in gmc_v7_0_soft_reset()
1215 tmp = RREG32(mmSRBM_SOFT_RESET); in gmc_v7_0_soft_reset()
1232 u32 tmp; in gmc_v7_0_vm_fault_interrupt_state() local
1243 tmp = RREG32(mmVM_CONTEXT0_CNTL); in gmc_v7_0_vm_fault_interrupt_state()
1244 tmp &= ~bits; in gmc_v7_0_vm_fault_interrupt_state()
1245 WREG32(mmVM_CONTEXT0_CNTL, tmp); in gmc_v7_0_vm_fault_interrupt_state()
1247 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v7_0_vm_fault_interrupt_state()
1248 tmp &= ~bits; in gmc_v7_0_vm_fault_interrupt_state()
1249 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v7_0_vm_fault_interrupt_state()
1253 tmp = RREG32(mmVM_CONTEXT0_CNTL); in gmc_v7_0_vm_fault_interrupt_state()
1254 tmp |= bits; in gmc_v7_0_vm_fault_interrupt_state()
1255 WREG32(mmVM_CONTEXT0_CNTL, tmp); in gmc_v7_0_vm_fault_interrupt_state()
1257 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v7_0_vm_fault_interrupt_state()
1258 tmp |= bits; in gmc_v7_0_vm_fault_interrupt_state()
1259 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v7_0_vm_fault_interrupt_state()