189 	uint32_t tmp;  in gfxhub_v2_0_init_tlb_regs()  local
192 	tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);  in gfxhub_v2_0_init_tlb_regs()
194 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);  in gfxhub_v2_0_init_tlb_regs()
195 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);  in gfxhub_v2_0_init_tlb_regs()
196 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,  in gfxhub_v2_0_init_tlb_regs()
198 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,  in gfxhub_v2_0_init_tlb_regs()
200 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);  in gfxhub_v2_0_init_tlb_regs()
201 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,  in gfxhub_v2_0_init_tlb_regs()
204 	WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);  in gfxhub_v2_0_init_tlb_regs()
209 	uint32_t tmp;  in gfxhub_v2_0_init_cache_regs()  local
216 	tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);  in gfxhub_v2_0_init_cache_regs()
217 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);  in gfxhub_v2_0_init_cache_regs()
218 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);  in gfxhub_v2_0_init_cache_regs()
219 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,  in gfxhub_v2_0_init_cache_regs()
222 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,  in gfxhub_v2_0_init_cache_regs()
224 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);  in gfxhub_v2_0_init_cache_regs()
225 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);  in gfxhub_v2_0_init_cache_regs()
226 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);  in gfxhub_v2_0_init_cache_regs()
227 	WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp);  in gfxhub_v2_0_init_cache_regs()
229 	tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2);  in gfxhub_v2_0_init_cache_regs()
230 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);  in gfxhub_v2_0_init_cache_regs()
231 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);  in gfxhub_v2_0_init_cache_regs()
232 	WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp);  in gfxhub_v2_0_init_cache_regs()
234 	tmp = mmGCVM_L2_CNTL3_DEFAULT;  in gfxhub_v2_0_init_cache_regs()
236 		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);  in gfxhub_v2_0_init_cache_regs()
237 		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,  in gfxhub_v2_0_init_cache_regs()
240 		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);  in gfxhub_v2_0_init_cache_regs()
241 		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,  in gfxhub_v2_0_init_cache_regs()
244 	WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp);  in gfxhub_v2_0_init_cache_regs()
246 	tmp = mmGCVM_L2_CNTL4_DEFAULT;  in gfxhub_v2_0_init_cache_regs()
247 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);  in gfxhub_v2_0_init_cache_regs()
248 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);  in gfxhub_v2_0_init_cache_regs()
249 	WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp);  in gfxhub_v2_0_init_cache_regs()
251 	tmp = mmGCVM_L2_CNTL5_DEFAULT;  in gfxhub_v2_0_init_cache_regs()
252 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);  in gfxhub_v2_0_init_cache_regs()
253 	WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL5, tmp);  in gfxhub_v2_0_init_cache_regs()
258 	uint32_t tmp;  in gfxhub_v2_0_enable_system_domain()  local
260 	tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL);  in gfxhub_v2_0_enable_system_domain()
261 	tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);  in gfxhub_v2_0_enable_system_domain()
262 	tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);  in gfxhub_v2_0_enable_system_domain()
263 	tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,  in gfxhub_v2_0_enable_system_domain()
265 	WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL, tmp);  in gfxhub_v2_0_enable_system_domain()
289 	uint32_t tmp;  in gfxhub_v2_0_setup_vmid_config()  local
292 		tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i);  in gfxhub_v2_0_setup_vmid_config()
293 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);  in gfxhub_v2_0_setup_vmid_config()
294 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,  in gfxhub_v2_0_setup_vmid_config()
296 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v2_0_setup_vmid_config()
298 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v2_0_setup_vmid_config()
300 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v2_0_setup_vmid_config()
302 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v2_0_setup_vmid_config()
304 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v2_0_setup_vmid_config()
306 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v2_0_setup_vmid_config()
308 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v2_0_setup_vmid_config()
310 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v2_0_setup_vmid_config()
314 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v2_0_setup_vmid_config()
318 				    i * hub->ctx_distance, tmp);  in gfxhub_v2_0_setup_vmid_config()
364 	u32 tmp;  in gfxhub_v2_0_gart_disable()  local
373 	tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);  in gfxhub_v2_0_gart_disable()
374 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);  in gfxhub_v2_0_gart_disable()
375 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,  in gfxhub_v2_0_gart_disable()
377 	WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);  in gfxhub_v2_0_gart_disable()
395 	u32 tmp;  in gfxhub_v2_0_set_fault_enable_default()  local
396 	tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);  in gfxhub_v2_0_set_fault_enable_default()
397 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v2_0_set_fault_enable_default()
399 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v2_0_set_fault_enable_default()
401 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v2_0_set_fault_enable_default()
403 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v2_0_set_fault_enable_default()
405 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v2_0_set_fault_enable_default()
408 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v2_0_set_fault_enable_default()
410 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v2_0_set_fault_enable_default()
412 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v2_0_set_fault_enable_default()
414 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v2_0_set_fault_enable_default()
416 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v2_0_set_fault_enable_default()
418 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v2_0_set_fault_enable_default()
421 		tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v2_0_set_fault_enable_default()
423 		tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v2_0_set_fault_enable_default()
426 	WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp);  in gfxhub_v2_0_set_fault_enable_default()