121 	uint32_t tmp;  in gfxhub_v1_0_init_tlb_regs()  local
124 	tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);  in gfxhub_v1_0_init_tlb_regs()
126 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);  in gfxhub_v1_0_init_tlb_regs()
127 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);  in gfxhub_v1_0_init_tlb_regs()
128 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,  in gfxhub_v1_0_init_tlb_regs()
130 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,  in gfxhub_v1_0_init_tlb_regs()
132 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);  in gfxhub_v1_0_init_tlb_regs()
133 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,  in gfxhub_v1_0_init_tlb_regs()
135 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);  in gfxhub_v1_0_init_tlb_regs()
137 	WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);  in gfxhub_v1_0_init_tlb_regs()
142 	uint32_t tmp;  in gfxhub_v1_0_init_cache_regs()  local
145 	tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL);  in gfxhub_v1_0_init_cache_regs()
146 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);  in gfxhub_v1_0_init_cache_regs()
147 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);  in gfxhub_v1_0_init_cache_regs()
149 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,  in gfxhub_v1_0_init_cache_regs()
151 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);  in gfxhub_v1_0_init_cache_regs()
152 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);  in gfxhub_v1_0_init_cache_regs()
153 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);  in gfxhub_v1_0_init_cache_regs()
154 	WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL, tmp);  in gfxhub_v1_0_init_cache_regs()
156 	tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2);  in gfxhub_v1_0_init_cache_regs()
157 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);  in gfxhub_v1_0_init_cache_regs()
158 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);  in gfxhub_v1_0_init_cache_regs()
159 	WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL2, tmp);  in gfxhub_v1_0_init_cache_regs()
161 	tmp = mmVM_L2_CNTL3_DEFAULT;  in gfxhub_v1_0_init_cache_regs()
163 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);  in gfxhub_v1_0_init_cache_regs()
164 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,  in gfxhub_v1_0_init_cache_regs()
167 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);  in gfxhub_v1_0_init_cache_regs()
168 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,  in gfxhub_v1_0_init_cache_regs()
171 	WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL3, tmp);  in gfxhub_v1_0_init_cache_regs()
173 	tmp = mmVM_L2_CNTL4_DEFAULT;  in gfxhub_v1_0_init_cache_regs()
174 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);  in gfxhub_v1_0_init_cache_regs()
175 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);  in gfxhub_v1_0_init_cache_regs()
176 	WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL4, tmp);  in gfxhub_v1_0_init_cache_regs()
181 	uint32_t tmp;  in gfxhub_v1_0_enable_system_domain()  local
183 	tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL);  in gfxhub_v1_0_enable_system_domain()
184 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);  in gfxhub_v1_0_enable_system_domain()
185 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);  in gfxhub_v1_0_enable_system_domain()
186 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,  in gfxhub_v1_0_enable_system_domain()
188 	WREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL, tmp);  in gfxhub_v1_0_enable_system_domain()
212 	uint32_t tmp;  in gfxhub_v1_0_setup_vmid_config()  local
223 		tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i);  in gfxhub_v1_0_setup_vmid_config()
224 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);  in gfxhub_v1_0_setup_vmid_config()
225 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,  in gfxhub_v1_0_setup_vmid_config()
227 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
229 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
232 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
234 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
236 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
238 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
240 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
242 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
246 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
250 				    i * hub->ctx_distance, tmp);  in gfxhub_v1_0_setup_vmid_config()
310 	u32 tmp;  in gfxhub_v1_0_gart_disable()  local
319 	tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);  in gfxhub_v1_0_gart_disable()
320 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);  in gfxhub_v1_0_gart_disable()
321 	tmp = REG_SET_FIELD(tmp,  in gfxhub_v1_0_gart_disable()
325 	WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);  in gfxhub_v1_0_gart_disable()
341 	u32 tmp;  in gfxhub_v1_0_set_fault_enable_default()  local
342 	tmp = RREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);  in gfxhub_v1_0_set_fault_enable_default()
343 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
345 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
347 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
349 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
351 	tmp = REG_SET_FIELD(tmp,  in gfxhub_v1_0_set_fault_enable_default()
355 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
357 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
359 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
361 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
363 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
365 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
368 		tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
370 		tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
373 	WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp);  in gfxhub_v1_0_set_fault_enable_default()