47 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =  variable
183 	return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) & 0x3fffc) >> 2;  in cik_sdma_ring_get_wptr()
197 	WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me],  in cik_sdma_ring_set_wptr()
318 		rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);  in cik_sdma_gfx_stop()
320 		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);  in cik_sdma_gfx_stop()
321 		WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0);  in cik_sdma_gfx_stop()
375 		f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);  in cik_ctx_switch_enable()
380 				WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i],  in cik_ctx_switch_enable()
382 				WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i],  in cik_ctx_switch_enable()
390 		WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);  in cik_ctx_switch_enable()
413 		me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);  in cik_sdma_enable()
418 		WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl);  in cik_sdma_enable()
446 			WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);  in cik_sdma_gfx_resume()
447 			WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);  in cik_sdma_gfx_resume()
453 		WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],  in cik_sdma_gfx_resume()
456 		WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);  in cik_sdma_gfx_resume()
457 		WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);  in cik_sdma_gfx_resume()
466 		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);  in cik_sdma_gfx_resume()
469 		WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);  in cik_sdma_gfx_resume()
470 		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);  in cik_sdma_gfx_resume()
471 		WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);  in cik_sdma_gfx_resume()
472 		WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);  in cik_sdma_gfx_resume()
475 		WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],  in cik_sdma_gfx_resume()
477 		WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],  in cik_sdma_gfx_resume()
482 		WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);  in cik_sdma_gfx_resume()
483 		WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);  in cik_sdma_gfx_resume()
486 		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2);  in cik_sdma_gfx_resume()
489 		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i],  in cik_sdma_gfx_resume()
497 		WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);  in cik_sdma_gfx_resume()
561 		WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);  in cik_sdma_load_microcode()
563 			WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));  in cik_sdma_load_microcode()
564 		WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);  in cik_sdma_load_microcode()