Lines Matching refs:gpu_addr
234 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ in cik_sdma_ring_emit_ib()
235 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff); in cik_sdma_ring_emit_ib()
476 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); in cik_sdma_gfx_resume()
478 ((adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC)); in cik_sdma_gfx_resume()
482 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); in cik_sdma_gfx_resume()
483 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); in cik_sdma_gfx_resume()
618 u64 gpu_addr; in cik_sdma_ring_test_ring() local
624 gpu_addr = adev->wb.gpu_addr + (index * 4); in cik_sdma_ring_test_ring()
633 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in cik_sdma_ring_test_ring()
634 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); in cik_sdma_ring_test_ring()
669 u64 gpu_addr; in cik_sdma_ring_test_ib() local
676 gpu_addr = adev->wb.gpu_addr + (index * 4); in cik_sdma_ring_test_ib()
687 ib.ptr[1] = lower_32_bits(gpu_addr); in cik_sdma_ring_test_ib()
688 ib.ptr[2] = upper_32_bits(gpu_addr); in cik_sdma_ring_test_ib()
834 uint64_t addr = ring->fence_drv.gpu_addr; in cik_sdma_ring_emit_pipeline_sync()