Lines Matching refs:inst_idx
70 #define RREG32_SOC15_DPG_MODE_1_0(ip, inst_idx, reg, mask, sram_sel) \ argument
71 ({ WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \
72 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \
74 ((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) \
77 RREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA); \
80 #define WREG32_SOC15_DPG_MODE_1_0(ip, inst_idx, reg, value, mask, sram_sel) \ argument
82 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA, value); \
83 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \
84 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \
86 ((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) \
91 #define SOC15_DPG_MODE_OFFSET(ip, inst_idx, reg) \ argument
96 addr = (adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg); \
124 #define RREG32_SOC15_DPG_MODE(inst_idx, offset, mask_en) \ argument
126 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_CTL, \
130 RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_DATA); \
133 #define WREG32_SOC15_DPG_MODE(inst_idx, offset, value, mask_en, indirect) \ argument
136 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_DATA, value); \
137 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_CTL, \
142 *adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = offset; \
143 *adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = value; \
228 int inst_idx, struct dpg_pause_state *new_state);