134 static int __update_table_header(struct amdgpu_ras_eeprom_control *control,  in __update_table_header()  argument
138 	struct amdgpu_device *adev = to_amdgpu_device(control);  in __update_table_header()
148 	__encode_table_header_to_buff(&control->tbl_hdr, buff + EEPROM_ADDRESS_SIZE);  in __update_table_header()
150 	msg.addr = control->i2c_address;  in __update_table_header()
159 static uint32_t  __calc_hdr_byte_sum(struct amdgpu_ras_eeprom_control *control)  in __calc_hdr_byte_sum()  argument
165 	for (i = 0; i < sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum); i++)  in __calc_hdr_byte_sum()
166 		tbl_sum += *(((unsigned char *)&control->tbl_hdr) + i);  in __calc_hdr_byte_sum()
189 static inline uint32_t  __calc_tbl_byte_sum(struct amdgpu_ras_eeprom_control *control,  in __calc_tbl_byte_sum()  argument
192 	return __calc_hdr_byte_sum(control) + __calc_recs_byte_sum(records, num);  in __calc_tbl_byte_sum()
196 static void __update_tbl_checksum(struct amdgpu_ras_eeprom_control *control,  in __update_tbl_checksum()  argument
208 	control->tbl_byte_sum -= old_hdr_byte_sum;  in __update_tbl_checksum()
209 	control->tbl_byte_sum += __calc_tbl_byte_sum(control, records, num);  in __update_tbl_checksum()
211 	control->tbl_hdr.checksum = 256 - (control->tbl_byte_sum % 256);  in __update_tbl_checksum()
215 static bool __validate_tbl_checksum(struct amdgpu_ras_eeprom_control *control,  in __validate_tbl_checksum()  argument
218 	control->tbl_byte_sum = __calc_tbl_byte_sum(control, records, num);  in __validate_tbl_checksum()
220 	if (control->tbl_hdr.checksum + (control->tbl_byte_sum % 256) != 256) {  in __validate_tbl_checksum()
221 		DRM_WARN("Checksum mismatch, checksum: %u ", control->tbl_hdr.checksum);  in __validate_tbl_checksum()
229 				struct amdgpu_ras_eeprom_control *control,  in amdgpu_ras_eeprom_correct_header_tag()  argument
233 	struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;  in amdgpu_ras_eeprom_correct_header_tag()
238 	mutex_lock(&control->tbl_mutex);  in amdgpu_ras_eeprom_correct_header_tag()
240 	ret = __update_table_header(control, buff);  in amdgpu_ras_eeprom_correct_header_tag()
241 	mutex_unlock(&control->tbl_mutex);  in amdgpu_ras_eeprom_correct_header_tag()
246 int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control)  in amdgpu_ras_eeprom_reset_table()  argument
249 	struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;  in amdgpu_ras_eeprom_reset_table()
252 	mutex_lock(&control->tbl_mutex);  in amdgpu_ras_eeprom_reset_table()
259 	control->tbl_byte_sum = 0;  in amdgpu_ras_eeprom_reset_table()
260 	__update_tbl_checksum(control, NULL, 0, 0);  in amdgpu_ras_eeprom_reset_table()
261 	control->next_addr = EEPROM_RECORD_START;  in amdgpu_ras_eeprom_reset_table()
263 	ret = __update_table_header(control, buff);  in amdgpu_ras_eeprom_reset_table()
265 	mutex_unlock(&control->tbl_mutex);  in amdgpu_ras_eeprom_reset_table()
271 int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control,  in amdgpu_ras_eeprom_init()  argument
275 	struct amdgpu_device *adev = to_amdgpu_device(control);  in amdgpu_ras_eeprom_init()
277 	struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;  in amdgpu_ras_eeprom_init()
295 	if (!__get_eeprom_i2c_addr(adev, &control->i2c_address))  in amdgpu_ras_eeprom_init()
298 	mutex_init(&control->tbl_mutex);  in amdgpu_ras_eeprom_init()
300 	msg.addr = control->i2c_address;  in amdgpu_ras_eeprom_init()
311 		control->num_recs = (hdr->tbl_size - EEPROM_TABLE_HEADER_SIZE) /  in amdgpu_ras_eeprom_init()
313 		control->tbl_byte_sum = __calc_hdr_byte_sum(control);  in amdgpu_ras_eeprom_init()
314 		control->next_addr = EEPROM_RECORD_START;  in amdgpu_ras_eeprom_init()
317 				 control->num_recs);  in amdgpu_ras_eeprom_init()
321 		if (ras->bad_page_cnt_threshold > control->num_recs) {  in amdgpu_ras_eeprom_init()
324 			ret = amdgpu_ras_eeprom_correct_header_tag(control,  in amdgpu_ras_eeprom_init()
334 		ret = amdgpu_ras_eeprom_reset_table(control);  in amdgpu_ras_eeprom_init()
340 static void __encode_table_record_to_buff(struct amdgpu_ras_eeprom_control *control,  in __encode_table_record_to_buff()  argument
367 static void __decode_table_record_from_buff(struct amdgpu_ras_eeprom_control *control,  in __decode_table_record_from_buff()  argument
428 				struct amdgpu_ras_eeprom_control *control,  in amdgpu_ras_eeprom_check_err_threshold()  argument
431 	struct amdgpu_device *adev = to_amdgpu_device(control);  in amdgpu_ras_eeprom_check_err_threshold()
434 	struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;  in amdgpu_ras_eeprom_check_err_threshold()
436 			.addr = control->i2c_address,  in amdgpu_ras_eeprom_check_err_threshold()
449 	mutex_lock(&control->tbl_mutex);  in amdgpu_ras_eeprom_check_err_threshold()
466 	mutex_unlock(&control->tbl_mutex);  in amdgpu_ras_eeprom_check_err_threshold()
470 int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control *control,  in amdgpu_ras_eeprom_process_recods()  argument
480 	struct amdgpu_device *adev = to_amdgpu_device(control);  in amdgpu_ras_eeprom_process_recods()
491 	mutex_lock(&control->tbl_mutex);  in amdgpu_ras_eeprom_process_recods()
511 		((control->num_recs + num) >= ras->bad_page_cnt_threshold)) {  in amdgpu_ras_eeprom_process_recods()
514 			control->num_recs + num, ras->bad_page_cnt_threshold);  in amdgpu_ras_eeprom_process_recods()
515 		control->tbl_hdr.header = EEPROM_TABLE_HDR_BAD;  in amdgpu_ras_eeprom_process_recods()
520 	if (write && (control->next_addr + EEPROM_TABLE_RECORD_SIZE * num > EEPROM_SIZE_BYTES))  in amdgpu_ras_eeprom_process_recods()
521 		control->next_addr = EEPROM_RECORD_START;  in amdgpu_ras_eeprom_process_recods()
533 		control->next_addr = __correct_eeprom_dest_address(control->next_addr);  in amdgpu_ras_eeprom_process_recods()
539 		msg->addr = control->i2c_address |  in amdgpu_ras_eeprom_process_recods()
540 			        ((control->next_addr & EEPROM_ADDR_MSB_MASK) >> 15);  in amdgpu_ras_eeprom_process_recods()
546 		buff[0] = ((control->next_addr >> 8) & 0xff);  in amdgpu_ras_eeprom_process_recods()
547 		buff[1] = (control->next_addr & 0xff);  in amdgpu_ras_eeprom_process_recods()
551 			__encode_table_record_to_buff(control, record, buff + EEPROM_ADDRESS_SIZE);  in amdgpu_ras_eeprom_process_recods()
557 		control->next_addr += EEPROM_TABLE_RECORD_SIZE;  in amdgpu_ras_eeprom_process_recods()
574 			__decode_table_record_from_buff(control, record, buff + EEPROM_ADDRESS_SIZE);  in amdgpu_ras_eeprom_process_recods()
579 		uint32_t old_hdr_byte_sum = __calc_hdr_byte_sum(control);  in amdgpu_ras_eeprom_process_recods()
588 		control->num_recs += num;  in amdgpu_ras_eeprom_process_recods()
589 		control->num_recs %= EEPROM_MAX_RECORD_NUM;  in amdgpu_ras_eeprom_process_recods()
590 		control->tbl_hdr.tbl_size += EEPROM_TABLE_RECORD_SIZE * num;  in amdgpu_ras_eeprom_process_recods()
591 		if (control->tbl_hdr.tbl_size > EEPROM_SIZE_BYTES)  in amdgpu_ras_eeprom_process_recods()
592 			control->tbl_hdr.tbl_size = EEPROM_TABLE_HEADER_SIZE +  in amdgpu_ras_eeprom_process_recods()
593 			control->num_recs * EEPROM_TABLE_RECORD_SIZE;  in amdgpu_ras_eeprom_process_recods()
595 		__update_tbl_checksum(control, records, num, old_hdr_byte_sum);  in amdgpu_ras_eeprom_process_recods()
597 		__update_table_header(control, buffs);  in amdgpu_ras_eeprom_process_recods()
612 	} else if (!__validate_tbl_checksum(control, records, num)) {  in amdgpu_ras_eeprom_process_recods()
624 	mutex_unlock(&control->tbl_mutex);  in amdgpu_ras_eeprom_process_recods()
636 void amdgpu_ras_eeprom_test(struct amdgpu_ras_eeprom_control *control)
649 	if (!amdgpu_ras_eeprom_process_recods(control, recs, true, 1)) {
653 		control->next_addr = EEPROM_RECORD_START;
655 		if (!amdgpu_ras_eeprom_process_recods(control, recs, false, 1)) {