260 	bp.resv = NULL;  in amdgpu_bo_create_reserved()
529 		.resv = bp->resv,  in amdgpu_bo_do_create()
590 				 NULL, bp->resv, &amdgpu_bo_destroy);  in amdgpu_bo_do_create()
606 		r = amdgpu_fill_buffer(bo, 0, bo->tbo.base.resv, &fence);  in amdgpu_bo_do_create()
615 	if (!bp->resv)  in amdgpu_bo_do_create()
628 	if (!bp->resv)  in amdgpu_bo_do_create()
629 		dma_resv_unlock(bo->tbo.base.resv);  in amdgpu_bo_do_create()
650 	bp.resv = bo->tbo.base.resv;  in amdgpu_bo_create_shadow()
690 		if (!bp->resv)  in amdgpu_bo_create()
691 			WARN_ON(dma_resv_lock((*bo_ptr)->tbo.base.resv,  in amdgpu_bo_create()
696 		if (!bp->resv)  in amdgpu_bo_create()
697 			dma_resv_unlock((*bo_ptr)->tbo.base.resv);  in amdgpu_bo_create()
794 	r = dma_resv_wait_timeout_rcu(bo->tbo.base.resv, false, false,  in amdgpu_bo_kmap()
1182 	dma_resv_assert_held(bo->tbo.base.resv);  in amdgpu_bo_get_tiling_flags()
1333 			&& bo->base.resv != &bo->base._resv);  in amdgpu_bo_release_notify()
1334 	if (bo->base.resv == &bo->base._resv)  in amdgpu_bo_release_notify()
1341 	dma_resv_lock(bo->base.resv, NULL);  in amdgpu_bo_release_notify()
1343 	r = amdgpu_fill_buffer(abo, AMDGPU_POISON, bo->base.resv, &fence);  in amdgpu_bo_release_notify()
1349 	dma_resv_unlock(bo->base.resv);  in amdgpu_bo_release_notify()
1424 	struct dma_resv *resv = bo->tbo.base.resv;  in amdgpu_bo_fence()  local
1427 		dma_resv_add_shared_fence(resv, fence);  in amdgpu_bo_fence()
1429 		dma_resv_add_excl_fence(resv, fence);  in amdgpu_bo_fence()
1446 int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv,  in amdgpu_bo_sync_wait_resv()  argument
1454 	amdgpu_sync_resv(adev, &sync, resv, sync_mode, owner);  in amdgpu_bo_sync_wait_resv()
1474 	return amdgpu_bo_sync_wait_resv(adev, bo->tbo.base.resv,  in amdgpu_bo_sync_wait()
1491 	WARN_ON_ONCE(!dma_resv_is_locked(bo->tbo.base.resv) &&  in amdgpu_bo_gpu_offset()