Lines Matching refs:amdgpu_device

203 	uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
204 	void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num,
206 	void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd,
208 	void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd,
211 	void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd,
214 	void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe,
216 	int (*ras_error_inject)(struct amdgpu_device *adev, void *inject_if);
217 	int (*query_ras_error_count) (struct amdgpu_device *adev, void *ras_error_status);
218 	void (*reset_ras_error_count) (struct amdgpu_device *adev);
219 	void (*init_spm_golden)(struct amdgpu_device *adev);
220 	void (*query_ras_error_status) (struct amdgpu_device *adev);
344 int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg);
345 void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg);
350 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
356 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev);
357 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
360 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
362 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev);
363 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev);
364 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev);
366 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev);
367 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev);
369 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec,
371 void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
373 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec,
375 bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
377 int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me,
379 void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
381 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me,
383 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
384 int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value);
385 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev);
386 void amdgpu_gfx_ras_fini(struct amdgpu_device *adev);
387 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
390 int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
393 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
394 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);