2  * Copyright 2007-8 Advanced Micro Devices, Inc.
50 	schedule_work(&work->flip_work.work);  in amdgpu_display_flip_callback()
63 	if (!dma_fence_add_callback(fence, &work->cb,  in amdgpu_display_flip_handle_fence()
77 	struct amdgpu_device *adev = work->adev;  in amdgpu_display_flip_work_func()
78 	struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id];  in amdgpu_display_flip_work_func()
80 	struct drm_crtc *crtc = &amdgpu_crtc->base;  in amdgpu_display_flip_work_func()
85 	if (amdgpu_display_flip_handle_fence(work, &work->excl))  in amdgpu_display_flip_work_func()
88 	for (i = 0; i < work->shared_count; ++i)  in amdgpu_display_flip_work_func()
89 		if (amdgpu_display_flip_handle_fence(work, &work->shared[i]))  in amdgpu_display_flip_work_func()
95 	if (amdgpu_crtc->enabled &&  in amdgpu_display_flip_work_func()
96 	    (amdgpu_display_get_crtc_scanoutpos(adev_to_drm(adev), work->crtc_id, 0,  in amdgpu_display_flip_work_func()
98 						&crtc->hwmode)  in amdgpu_display_flip_work_func()
101 	    (int)(work->target_vblank -  in amdgpu_display_flip_work_func()
103 		schedule_delayed_work(&work->flip_work, usecs_to_jiffies(1000));  in amdgpu_display_flip_work_func()
108 	spin_lock_irqsave(&crtc->dev->event_lock, flags);  in amdgpu_display_flip_work_func()
111 	adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async);  in amdgpu_display_flip_work_func()
114 	amdgpu_crtc->pflip_status = AMDGPU_FLIP_SUBMITTED;  in amdgpu_display_flip_work_func()
115 	spin_unlock_irqrestore(&crtc->dev->event_lock, flags);  in amdgpu_display_flip_work_func()
119 					 amdgpu_crtc->crtc_id, amdgpu_crtc, work);  in amdgpu_display_flip_work_func()
133 	r = amdgpu_bo_reserve(work->old_abo, true);  in amdgpu_display_unpin_work_func()
135 		r = amdgpu_bo_unpin(work->old_abo);  in amdgpu_display_unpin_work_func()
139 		amdgpu_bo_unreserve(work->old_abo);  in amdgpu_display_unpin_work_func()
143 	amdgpu_bo_unref(&work->old_abo);  in amdgpu_display_unpin_work_func()
144 	kfree(work->shared);  in amdgpu_display_unpin_work_func()
151 				uint32_t page_flip_flags, uint32_t target,  in amdgpu_display_crtc_page_flip_target()  argument
154 	struct drm_device *dev = crtc->dev;  in amdgpu_display_crtc_page_flip_target()
166 		return -ENOMEM;  in amdgpu_display_crtc_page_flip_target()
168 	INIT_DELAYED_WORK(&work->flip_work, amdgpu_display_flip_work_func);  in amdgpu_display_crtc_page_flip_target()
169 	INIT_WORK(&work->unpin_work, amdgpu_display_unpin_work_func);  in amdgpu_display_crtc_page_flip_target()
171 	work->event = event;  in amdgpu_display_crtc_page_flip_target()
172 	work->adev = adev;  in amdgpu_display_crtc_page_flip_target()
173 	work->crtc_id = amdgpu_crtc->crtc_id;  in amdgpu_display_crtc_page_flip_target()
174 	work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;  in amdgpu_display_crtc_page_flip_target()
177 	obj = crtc->primary->fb->obj[0];  in amdgpu_display_crtc_page_flip_target()
180 	work->old_abo = gem_to_amdgpu_bo(obj);  in amdgpu_display_crtc_page_flip_target()
181 	amdgpu_bo_ref(work->old_abo);  in amdgpu_display_crtc_page_flip_target()
183 	obj = fb->obj[0];  in amdgpu_display_crtc_page_flip_target()
193 	if (!adev->enable_virtual_display) {  in amdgpu_display_crtc_page_flip_target()
195 				  amdgpu_display_supported_domains(adev, new_abo->flags));  in amdgpu_display_crtc_page_flip_target()
202 	r = amdgpu_ttm_alloc_gart(&new_abo->tbo);  in amdgpu_display_crtc_page_flip_target()
208 	r = dma_resv_get_fences_rcu(new_abo->tbo.base.resv, &work->excl,  in amdgpu_display_crtc_page_flip_target()
209 					      &work->shared_count,  in amdgpu_display_crtc_page_flip_target()
210 					      &work->shared);  in amdgpu_display_crtc_page_flip_target()
219 	if (!adev->enable_virtual_display)  in amdgpu_display_crtc_page_flip_target()
220 		work->base = amdgpu_bo_gpu_offset(new_abo);  in amdgpu_display_crtc_page_flip_target()
221 	work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +  in amdgpu_display_crtc_page_flip_target()
225 	spin_lock_irqsave(&crtc->dev->event_lock, flags);  in amdgpu_display_crtc_page_flip_target()
226 	if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) {  in amdgpu_display_crtc_page_flip_target()
228 		spin_unlock_irqrestore(&crtc->dev->event_lock, flags);  in amdgpu_display_crtc_page_flip_target()
229 		r = -EBUSY;  in amdgpu_display_crtc_page_flip_target()
233 	amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING;  in amdgpu_display_crtc_page_flip_target()
234 	amdgpu_crtc->pflip_works = work;  in amdgpu_display_crtc_page_flip_target()
238 					 amdgpu_crtc->crtc_id, amdgpu_crtc, work);  in amdgpu_display_crtc_page_flip_target()
240 	crtc->primary->fb = fb;  in amdgpu_display_crtc_page_flip_target()
241 	spin_unlock_irqrestore(&crtc->dev->event_lock, flags);  in amdgpu_display_crtc_page_flip_target()
242 	amdgpu_display_flip_work_func(&work->flip_work.work);  in amdgpu_display_crtc_page_flip_target()
251 	if (!adev->enable_virtual_display)  in amdgpu_display_crtc_page_flip_target()
259 	amdgpu_bo_unref(&work->old_abo);  in amdgpu_display_crtc_page_flip_target()
260 	dma_fence_put(work->excl);  in amdgpu_display_crtc_page_flip_target()
261 	for (i = 0; i < work->shared_count; ++i)  in amdgpu_display_crtc_page_flip_target()
262 		dma_fence_put(work->shared[i]);  in amdgpu_display_crtc_page_flip_target()
263 	kfree(work->shared);  in amdgpu_display_crtc_page_flip_target()
278 	if (!set || !set->crtc)  in amdgpu_display_crtc_set_config()
279 		return -EINVAL;  in amdgpu_display_crtc_set_config()
281 	dev = set->crtc->dev;  in amdgpu_display_crtc_set_config()
283 	ret = pm_runtime_get_sync(dev->dev);  in amdgpu_display_crtc_set_config()
289 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)  in amdgpu_display_crtc_set_config()
290 		if (crtc->enabled)  in amdgpu_display_crtc_set_config()
293 	pm_runtime_mark_last_busy(dev->dev);  in amdgpu_display_crtc_set_config()
298 	if (active && !adev->have_disp_power_ref) {  in amdgpu_display_crtc_set_config()
299 		adev->have_disp_power_ref = true;  in amdgpu_display_crtc_set_config()
304 	if (!active && adev->have_disp_power_ref) {  in amdgpu_display_crtc_set_config()
305 		pm_runtime_put_autosuspend(dev->dev);  in amdgpu_display_crtc_set_config()
306 		adev->have_disp_power_ref = false;  in amdgpu_display_crtc_set_config()
311 	pm_runtime_put_autosuspend(dev->dev);  in amdgpu_display_crtc_set_config()
383 		DRM_INFO("  %s\n", connector->name);  in amdgpu_display_print_display_setup()
384 		if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE)  in amdgpu_display_print_display_setup()
385 			DRM_INFO("  %s\n", hpd_names[amdgpu_connector->hpd.hpd]);  in amdgpu_display_print_display_setup()
386 		if (amdgpu_connector->ddc_bus) {  in amdgpu_display_print_display_setup()
388 				 amdgpu_connector->ddc_bus->rec.mask_clk_reg,  in amdgpu_display_print_display_setup()
389 				 amdgpu_connector->ddc_bus->rec.mask_data_reg,  in amdgpu_display_print_display_setup()
390 				 amdgpu_connector->ddc_bus->rec.a_clk_reg,  in amdgpu_display_print_display_setup()
391 				 amdgpu_connector->ddc_bus->rec.a_data_reg,  in amdgpu_display_print_display_setup()
392 				 amdgpu_connector->ddc_bus->rec.en_clk_reg,  in amdgpu_display_print_display_setup()
393 				 amdgpu_connector->ddc_bus->rec.en_data_reg,  in amdgpu_display_print_display_setup()
394 				 amdgpu_connector->ddc_bus->rec.y_clk_reg,  in amdgpu_display_print_display_setup()
395 				 amdgpu_connector->ddc_bus->rec.y_data_reg);  in amdgpu_display_print_display_setup()
396 			if (amdgpu_connector->router.ddc_valid)  in amdgpu_display_print_display_setup()
398 					 amdgpu_connector->router.ddc_mux_control_pin,  in amdgpu_display_print_display_setup()
399 					 amdgpu_connector->router.ddc_mux_state);  in amdgpu_display_print_display_setup()
400 			if (amdgpu_connector->router.cd_valid)  in amdgpu_display_print_display_setup()
402 					 amdgpu_connector->router.cd_mux_control_pin,  in amdgpu_display_print_display_setup()
403 					 amdgpu_connector->router.cd_mux_state);  in amdgpu_display_print_display_setup()
405 			if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||  in amdgpu_display_print_display_setup()
406 			    connector->connector_type == DRM_MODE_CONNECTOR_DVII ||  in amdgpu_display_print_display_setup()
407 			    connector->connector_type == DRM_MODE_CONNECTOR_DVID ||  in amdgpu_display_print_display_setup()
408 			    connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||  in amdgpu_display_print_display_setup()
409 			    connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||  in amdgpu_display_print_display_setup()
410 			    connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)  in amdgpu_display_print_display_setup()
411 …DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");  in amdgpu_display_print_display_setup()
414 		list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {  in amdgpu_display_print_display_setup()
416 			devices = amdgpu_encoder->devices & amdgpu_connector->devices;  in amdgpu_display_print_display_setup()
419 					DRM_INFO("    CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);  in amdgpu_display_print_display_setup()
421 					DRM_INFO("    CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);  in amdgpu_display_print_display_setup()
423 					DRM_INFO("    LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);  in amdgpu_display_print_display_setup()
425 					DRM_INFO("    DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);  in amdgpu_display_print_display_setup()
427 					DRM_INFO("    DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);  in amdgpu_display_print_display_setup()
429 					DRM_INFO("    DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]);  in amdgpu_display_print_display_setup()
431 					DRM_INFO("    DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]);  in amdgpu_display_print_display_setup()
433 					DRM_INFO("    DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]);  in amdgpu_display_print_display_setup()
435 					DRM_INFO("    DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]);  in amdgpu_display_print_display_setup()
437 					DRM_INFO("    TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);  in amdgpu_display_print_display_setup()
439 					DRM_INFO("    CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]);  in amdgpu_display_print_display_setup()
473 	if (amdgpu_connector->router.ddc_valid)  in amdgpu_display_ddc_probe()
477 		ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2);  in amdgpu_display_ddc_probe()
479 		ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2);  in amdgpu_display_ddc_probe()
519 	    amdgpu_device_asic_has_dc_support(adev->asic_type)) {  in amdgpu_display_supported_domains()
520 		switch (adev->asic_type) {  in amdgpu_display_supported_domains()
527 			if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||  in amdgpu_display_supported_domains()
528 			    (adev->apu_flags & AMD_APU_IS_PICASSO))  in amdgpu_display_supported_domains()
546 	rfb->base.obj[0] = obj;  in amdgpu_display_framebuffer_init()
547 	drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd);  in amdgpu_display_framebuffer_init()
548 	ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);  in amdgpu_display_framebuffer_init()
550 		rfb->base.obj[0] = NULL;  in amdgpu_display_framebuffer_init()
565 	obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);  in amdgpu_display_user_framebuffer_create()
567 		dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "  in amdgpu_display_user_framebuffer_create()
568 			"can't create framebuffer\n", mode_cmd->handles[0]);  in amdgpu_display_user_framebuffer_create()
569 		return ERR_PTR(-ENOENT);  in amdgpu_display_user_framebuffer_create()
572 	/* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */  in amdgpu_display_user_framebuffer_create()
573 	if (obj->import_attach) {  in amdgpu_display_user_framebuffer_create()
575 		return ERR_PTR(-EINVAL);  in amdgpu_display_user_framebuffer_create()
581 		return ERR_PTR(-ENOMEM);  in amdgpu_display_user_framebuffer_create()
591 	return &amdgpu_fb->base;  in amdgpu_display_user_framebuffer_create()
621 	adev->mode_info.coherent_mode_property =  in amdgpu_display_modeset_create_props()
623 	if (!adev->mode_info.coherent_mode_property)  in amdgpu_display_modeset_create_props()
624 		return -ENOMEM;  in amdgpu_display_modeset_create_props()
626 	adev->mode_info.load_detect_property =  in amdgpu_display_modeset_create_props()
628 	if (!adev->mode_info.load_detect_property)  in amdgpu_display_modeset_create_props()
629 		return -ENOMEM;  in amdgpu_display_modeset_create_props()
634 	adev->mode_info.underscan_property =  in amdgpu_display_modeset_create_props()
639 	adev->mode_info.underscan_hborder_property =  in amdgpu_display_modeset_create_props()
642 	if (!adev->mode_info.underscan_hborder_property)  in amdgpu_display_modeset_create_props()
643 		return -ENOMEM;  in amdgpu_display_modeset_create_props()
645 	adev->mode_info.underscan_vborder_property =  in amdgpu_display_modeset_create_props()
648 	if (!adev->mode_info.underscan_vborder_property)  in amdgpu_display_modeset_create_props()
649 		return -ENOMEM;  in amdgpu_display_modeset_create_props()
652 	adev->mode_info.audio_property =  in amdgpu_display_modeset_create_props()
658 	adev->mode_info.dither_property =  in amdgpu_display_modeset_create_props()
664 		adev->mode_info.abm_level_property =  in amdgpu_display_modeset_create_props()
667 		if (!adev->mode_info.abm_level_property)  in amdgpu_display_modeset_create_props()
668 			return -ENOMEM;  in amdgpu_display_modeset_create_props()
678 		adev->mode_info.disp_priority = 0;  in amdgpu_display_update_priority()
680 		adev->mode_info.disp_priority = amdgpu_disp_priority;  in amdgpu_display_update_priority()
687 	if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */  in amdgpu_display_is_hdtv_mode()
688 	    (mode->vdisplay == 576) || /* 576p */  in amdgpu_display_is_hdtv_mode()
689 	    (mode->vdisplay == 720) || /* 720p */  in amdgpu_display_is_hdtv_mode()
690 	    (mode->vdisplay == 1080)) /* 1080p */  in amdgpu_display_is_hdtv_mode()
700 	struct drm_device *dev = crtc->dev;  in amdgpu_display_crtc_scaling_mode_fixup()
708 	amdgpu_crtc->h_border = 0;  in amdgpu_display_crtc_scaling_mode_fixup()
709 	amdgpu_crtc->v_border = 0;  in amdgpu_display_crtc_scaling_mode_fixup()
711 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {  in amdgpu_display_crtc_scaling_mode_fixup()
712 		if (encoder->crtc != crtc)  in amdgpu_display_crtc_scaling_mode_fixup()
718 		if (amdgpu_encoder->rmx_type == RMX_OFF)  in amdgpu_display_crtc_scaling_mode_fixup()
719 			amdgpu_crtc->rmx_type = RMX_OFF;  in amdgpu_display_crtc_scaling_mode_fixup()
720 		else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay ||  in amdgpu_display_crtc_scaling_mode_fixup()
721 			 mode->vdisplay < amdgpu_encoder->native_mode.vdisplay)  in amdgpu_display_crtc_scaling_mode_fixup()
722 			amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type;  in amdgpu_display_crtc_scaling_mode_fixup()
724 			amdgpu_crtc->rmx_type = RMX_OFF;  in amdgpu_display_crtc_scaling_mode_fixup()
726 		memcpy(&amdgpu_crtc->native_mode,  in amdgpu_display_crtc_scaling_mode_fixup()
727 		       &amdgpu_encoder->native_mode,  in amdgpu_display_crtc_scaling_mode_fixup()
729 		src_v = crtc->mode.vdisplay;  in amdgpu_display_crtc_scaling_mode_fixup()
730 		dst_v = amdgpu_crtc->native_mode.vdisplay;  in amdgpu_display_crtc_scaling_mode_fixup()
731 		src_h = crtc->mode.hdisplay;  in amdgpu_display_crtc_scaling_mode_fixup()
732 		dst_h = amdgpu_crtc->native_mode.hdisplay;  in amdgpu_display_crtc_scaling_mode_fixup()
735 		if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&  in amdgpu_display_crtc_scaling_mode_fixup()
736 		    ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) ||  in amdgpu_display_crtc_scaling_mode_fixup()
737 		     ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) &&  in amdgpu_display_crtc_scaling_mode_fixup()
740 			if (amdgpu_encoder->underscan_hborder != 0)  in amdgpu_display_crtc_scaling_mode_fixup()
741 				amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder;  in amdgpu_display_crtc_scaling_mode_fixup()
743 				amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16;  in amdgpu_display_crtc_scaling_mode_fixup()
744 			if (amdgpu_encoder->underscan_vborder != 0)  in amdgpu_display_crtc_scaling_mode_fixup()
745 				amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder;  in amdgpu_display_crtc_scaling_mode_fixup()
747 				amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16;  in amdgpu_display_crtc_scaling_mode_fixup()
748 			amdgpu_crtc->rmx_type = RMX_FULL;  in amdgpu_display_crtc_scaling_mode_fixup()
749 			src_v = crtc->mode.vdisplay;  in amdgpu_display_crtc_scaling_mode_fixup()
750 			dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2);  in amdgpu_display_crtc_scaling_mode_fixup()
751 			src_h = crtc->mode.hdisplay;  in amdgpu_display_crtc_scaling_mode_fixup()
752 			dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2);  in amdgpu_display_crtc_scaling_mode_fixup()
755 	if (amdgpu_crtc->rmx_type != RMX_OFF) {  in amdgpu_display_crtc_scaling_mode_fixup()
759 		amdgpu_crtc->vsc.full = dfixed_div(a, b);  in amdgpu_display_crtc_scaling_mode_fixup()
762 		amdgpu_crtc->hsc.full = dfixed_div(a, b);  in amdgpu_display_crtc_scaling_mode_fixup()
764 		amdgpu_crtc->vsc.full = dfixed_const(1);  in amdgpu_display_crtc_scaling_mode_fixup()
765 		amdgpu_crtc->hsc.full = dfixed_const(1);  in amdgpu_display_crtc_scaling_mode_fixup()
788  * \param *stime Target location for timestamp taken immediately before
790  * \param *etime Target location for timestamp taken immediately after
795  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
846 		vbl_start = mode->crtc_vdisplay;  in amdgpu_display_get_crtc_scanoutpos()
853 	    *hpos = *vpos - vbl_start;  in amdgpu_display_get_crtc_scanoutpos()
867 		vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;  in amdgpu_display_get_crtc_scanoutpos()
880 		*vpos -= vbl_start;  in amdgpu_display_get_crtc_scanoutpos()
892 		vtotal = mode->crtc_vtotal;  in amdgpu_display_get_crtc_scanoutpos()
895 		 * the vtotal value. Clamp to 0 to return -vbl_end instead  in amdgpu_display_get_crtc_scanoutpos()
898 		*vpos = (*vpos < vtotal) ? (*vpos - vtotal) : 0;  in amdgpu_display_get_crtc_scanoutpos()
902 	*vpos = *vpos - vbl_end;  in amdgpu_display_get_crtc_scanoutpos()
909 	if (crtc < 0 || crtc >= adev->mode_info.num_crtc)  in amdgpu_display_crtc_idx_to_irq_type()
935 	struct drm_device *dev = crtc->dev;  in amdgpu_crtc_get_scanout_position()
936 	unsigned int pipe = crtc->index;  in amdgpu_crtc_get_scanout_position()