439 	    adev->gfx.rlc.funcs &&  in amdgpu_mm_wreg_mmio_rlc()
440 	    adev->gfx.rlc.funcs->is_rlcg_access_range) {  in amdgpu_mm_wreg_mmio_rlc()
441 		if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))  in amdgpu_mm_wreg_mmio_rlc()
442 			return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v);  in amdgpu_mm_wreg_mmio_rlc()
1857 		adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);  in amdgpu_device_parse_gpu_info_fw()
1858 		adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);  in amdgpu_device_parse_gpu_info_fw()
1859 		adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);  in amdgpu_device_parse_gpu_info_fw()
1860 		adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);  in amdgpu_device_parse_gpu_info_fw()
1861 		adev->gfx.config.max_texture_channel_caches =  in amdgpu_device_parse_gpu_info_fw()
1863 		adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);  in amdgpu_device_parse_gpu_info_fw()
1864 		adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);  in amdgpu_device_parse_gpu_info_fw()
1865 		adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);  in amdgpu_device_parse_gpu_info_fw()
1866 		adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);  in amdgpu_device_parse_gpu_info_fw()
1867 		adev->gfx.config.double_offchip_lds_buf =  in amdgpu_device_parse_gpu_info_fw()
1869 		adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);  in amdgpu_device_parse_gpu_info_fw()
1870 		adev->gfx.cu_info.max_waves_per_simd =  in amdgpu_device_parse_gpu_info_fw()
1872 		adev->gfx.cu_info.max_scratch_slots_per_cu =  in amdgpu_device_parse_gpu_info_fw()
1874 		adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);  in amdgpu_device_parse_gpu_info_fw()
1879 			adev->gfx.config.num_sc_per_sh =  in amdgpu_device_parse_gpu_info_fw()
1881 			adev->gfx.config.num_packer_per_sc =  in amdgpu_device_parse_gpu_info_fw()
2621 		container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work);  in amdgpu_device_delay_enable_gfx_off()
2623 	mutex_lock(&adev->gfx.gfx_off_mutex);  in amdgpu_device_delay_enable_gfx_off()
2624 	if (!adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) {  in amdgpu_device_delay_enable_gfx_off()
2626 			adev->gfx.gfx_off_state = true;  in amdgpu_device_delay_enable_gfx_off()
2628 	mutex_unlock(&adev->gfx.gfx_off_mutex);  in amdgpu_device_delay_enable_gfx_off()
3194 	bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);  in amdgpu_device_init()
3222 	mutex_init(&adev->gfx.gpu_clock_mutex);  in amdgpu_device_init()
3224 	mutex_init(&adev->gfx.pipe_reserve_mutex);  in amdgpu_device_init()
3225 	mutex_init(&adev->gfx.gfx_off_mutex);  in amdgpu_device_init()
3254 	INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work,  in amdgpu_device_init()
3259 	adev->gfx.gfx_off_req_count = 1;  in amdgpu_device_init()
3444 			adev->gfx.config.max_shader_engines,  in amdgpu_device_init()
3445 			adev->gfx.config.max_sh_per_se,  in amdgpu_device_init()
3446 			adev->gfx.config.max_cu_per_sh,  in amdgpu_device_init()
3447 			adev->gfx.cu_info.number);  in amdgpu_device_init()