Lines Matching +full:0 +full:x90
22 #define SIO_LDSEL 0x07 /* Logical device select */
23 #define SIO_DEVID 0x20 /* Device ID (2 bytes) */
24 #define SIO_DEVREV 0x22 /* Device revision */
25 #define SIO_MANID 0x23 /* Fintek ID (2 bytes) */
27 #define SIO_LD_GPIO 0x06 /* GPIO logical device */
28 #define SIO_UNLOCK_KEY 0x87 /* Key to enable Super-I/O */
29 #define SIO_LOCK_KEY 0xAA /* Key to disable Super-I/O */
31 #define SIO_FINTEK_ID 0x1934 /* Manufacturer ID */
32 #define SIO_F71869_ID 0x0814 /* F71869 chipset ID */
33 #define SIO_F71869A_ID 0x1007 /* F71869A chipset ID */
34 #define SIO_F71882_ID 0x0541 /* F71882 chipset ID */
35 #define SIO_F71889_ID 0x0909 /* F71889 chipset ID */
36 #define SIO_F71889A_ID 0x1005 /* F71889A chipset ID */
37 #define SIO_F81866_ID 0x1010 /* F81866 chipset ID */
38 #define SIO_F81804_ID 0x1502 /* F81804 chipset ID, same for f81966 */
39 #define SIO_F81865_ID 0x0704 /* F81865 chipset ID */
113 pr_err(DRVNAME "I/O address 0x%04x already in use\n", base); in superio_enter()
121 return 0; in superio_enter()
167 #define gpio_dir(base) (base + 0)
170 /* Output mode register (0:open drain 1:push-pull). */
174 F7188X_GPIO_BANK(0, 6, 0xF0),
175 F7188X_GPIO_BANK(10, 8, 0xE0),
176 F7188X_GPIO_BANK(20, 8, 0xD0),
177 F7188X_GPIO_BANK(30, 8, 0xC0),
178 F7188X_GPIO_BANK(40, 8, 0xB0),
179 F7188X_GPIO_BANK(50, 5, 0xA0),
180 F7188X_GPIO_BANK(60, 6, 0x90),
184 F7188X_GPIO_BANK(0, 6, 0xF0),
185 F7188X_GPIO_BANK(10, 8, 0xE0),
186 F7188X_GPIO_BANK(20, 8, 0xD0),
187 F7188X_GPIO_BANK(30, 8, 0xC0),
188 F7188X_GPIO_BANK(40, 8, 0xB0),
189 F7188X_GPIO_BANK(50, 5, 0xA0),
190 F7188X_GPIO_BANK(60, 8, 0x90),
191 F7188X_GPIO_BANK(70, 8, 0x80),
195 F7188X_GPIO_BANK(0, 8, 0xF0),
196 F7188X_GPIO_BANK(10, 8, 0xE0),
197 F7188X_GPIO_BANK(20, 8, 0xD0),
198 F7188X_GPIO_BANK(30, 4, 0xC0),
199 F7188X_GPIO_BANK(40, 4, 0xB0),
203 F7188X_GPIO_BANK(0, 7, 0xF0),
204 F7188X_GPIO_BANK(10, 7, 0xE0),
205 F7188X_GPIO_BANK(20, 8, 0xD0),
206 F7188X_GPIO_BANK(30, 8, 0xC0),
207 F7188X_GPIO_BANK(40, 8, 0xB0),
208 F7188X_GPIO_BANK(50, 5, 0xA0),
209 F7188X_GPIO_BANK(60, 8, 0x90),
210 F7188X_GPIO_BANK(70, 8, 0x80),
214 F7188X_GPIO_BANK(0, 7, 0xF0),
215 F7188X_GPIO_BANK(10, 7, 0xE0),
216 F7188X_GPIO_BANK(20, 8, 0xD0),
217 F7188X_GPIO_BANK(30, 8, 0xC0),
218 F7188X_GPIO_BANK(40, 8, 0xB0),
219 F7188X_GPIO_BANK(50, 5, 0xA0),
220 F7188X_GPIO_BANK(60, 8, 0x90),
221 F7188X_GPIO_BANK(70, 8, 0x80),
225 F7188X_GPIO_BANK(0, 8, 0xF0),
226 F7188X_GPIO_BANK(10, 8, 0xE0),
227 F7188X_GPIO_BANK(20, 8, 0xD0),
228 F7188X_GPIO_BANK(30, 8, 0xC0),
229 F7188X_GPIO_BANK(40, 8, 0xB0),
230 F7188X_GPIO_BANK(50, 8, 0xA0),
231 F7188X_GPIO_BANK(60, 8, 0x90),
232 F7188X_GPIO_BANK(70, 8, 0x80),
233 F7188X_GPIO_BANK(80, 8, 0x88),
238 F7188X_GPIO_BANK(0, 8, 0xF0),
239 F7188X_GPIO_BANK(10, 8, 0xE0),
240 F7188X_GPIO_BANK(20, 8, 0xD0),
241 F7188X_GPIO_BANK(50, 8, 0xA0),
242 F7188X_GPIO_BANK(60, 8, 0x90),
243 F7188X_GPIO_BANK(70, 8, 0x80),
244 F7188X_GPIO_BANK(90, 8, 0x98),
248 F7188X_GPIO_BANK(0, 8, 0xF0),
249 F7188X_GPIO_BANK(10, 8, 0xE0),
250 F7188X_GPIO_BANK(20, 8, 0xD0),
251 F7188X_GPIO_BANK(30, 8, 0xC0),
252 F7188X_GPIO_BANK(40, 8, 0xB0),
253 F7188X_GPIO_BANK(50, 8, 0xA0),
254 F7188X_GPIO_BANK(60, 5, 0x90),
297 return 0; in f7188x_gpio_direction_in()
350 return 0; in f7188x_gpio_direction_out()
401 return 0; in f7188x_gpio_set_config()
460 for (i = 0; i < data->nr_bank; i++) { in f7188x_gpio_probe()
475 return 0; in f7188x_gpio_probe()
490 pr_debug(DRVNAME ": Not a Fintek device at 0x%08x\n", addr); in f7188x_find()
521 pr_info(DRVNAME ": Unsupported Fintek device 0x%04x\n", devid); in f7188x_find()
525 err = 0; in f7188x_find()
561 return 0; in f7188x_gpio_device_add()
587 if (f7188x_find(0x2e, &sio) && in f7188x_gpio_init()
588 f7188x_find(0x4e, &sio)) in f7188x_gpio_init()