32 static const u32 ctrl_base = 0x80000000;  variable
218 		opb_readl(aspeed, ctrl_base + FSI_MRESP0, &mresp0);  in check_errors()
219 		opb_readl(aspeed, ctrl_base + FSI_MSTAP0, &mstap0);  in check_errors()
220 		opb_readl(aspeed, ctrl_base + FSI_MESRB0, &mesrb0);  in check_errors()
232 		ret = opb_writel(aspeed, ctrl_base + FSI_MRESP0,  in check_errors()
324 		return opb_writel(aspeed, ctrl_base + FSI_MCENP0 + (4 * idx),  in aspeed_master_link_enable()
327 	ret = opb_writel(aspeed, ctrl_base + FSI_MSENP0 + (4 * idx), reg);  in aspeed_master_link_enable()
383 	opb_writel(aspeed, ctrl_base + FSI_MRESP0, reg);  in aspeed_master_init()
388 	opb_writel(aspeed, ctrl_base + FSI_MRESP0, reg);  in aspeed_master_init()
391 	opb_writel(aspeed, ctrl_base + FSI_MECTRL, reg);  in aspeed_master_init()
399 	opb_writel(aspeed, ctrl_base + FSI_MMODE, reg);  in aspeed_master_init()
402 	opb_writel(aspeed, ctrl_base + FSI_MDLYR, reg);  in aspeed_master_init()
405 	opb_writel(aspeed, ctrl_base + FSI_MSENP0, reg);  in aspeed_master_init()
410 	opb_writel(aspeed, ctrl_base + FSI_MCENP0, reg);  in aspeed_master_init()
412 	opb_readl(aspeed, ctrl_base + FSI_MAEB, NULL);  in aspeed_master_init()
415 	opb_writel(aspeed, ctrl_base + FSI_MRESP0, reg);  in aspeed_master_init()
417 	opb_readl(aspeed, ctrl_base + FSI_MLEVP0, NULL);  in aspeed_master_init()
421 	opb_writel(aspeed, ctrl_base + FSI_MRESB0, reg);  in aspeed_master_init()
424 	opb_writel(aspeed, ctrl_base + FSI_MRESB0, reg);  in aspeed_master_init()
560 	writel(ctrl_base, aspeed->base + OPB_CTRL_BASE);  in fsi_master_aspeed_probe()
577 	rc = opb_readl(aspeed, ctrl_base + FSI_MVER, &raw);  in fsi_master_aspeed_probe()