Lines Matching full:fpga
3 # FPGA framework configuration
6 menuconfig FPGA config
7 tristate "FPGA Configuration Framework"
10 kernel. The FPGA framework adds a FPGA manager class and FPGA
13 if FPGA
16 tristate "Altera SOCFPGA FPGA Manager"
19 FPGA manager driver support for Altera SOCFPGA.
26 FPGA manager driver support for Altera Arria10 SoCFPGA.
41 tristate "Altera FPGA Passive Serial over SPI"
45 FPGA manager driver support for Altera Arria/Cyclone/Stratix
49 tristate "Altera CvP FPGA Manager"
52 FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V,
56 tristate "Xilinx Zynq FPGA"
59 FPGA manager driver support for Xilinx Zynq FPGAs.
62 tristate "Intel Stratix10 SoC FPGA Manager"
65 FPGA manager driver support for the Intel Stratix10 SoC.
71 FPGA manager driver support for Xilinx FPGA configuration
78 FPGA manager driver support for Lattice iCE40 FPGAs over SPI.
84 FPGA manager driver support for Lattice MachXO2 configuration
88 tristate "Technologic Systems TS-73xx SBC FPGA Manager"
91 FPGA manager driver support for the Altera Cyclone II FPGA
95 tristate "FPGA Bridge Framework"
101 tristate "Altera SoCFPGA FPGA Bridges"
104 Say Y to enable drivers for FPGA bridges for Altera SOCFPGA
108 tristate "Altera FPGA Freeze Bridge"
111 Say Y to enable drivers for Altera FPGA Freeze bridges. A
112 freeze bridge is a bridge that exists in the FPGA fabric to
113 isolate one region of the FPGA from the busses while that
122 The PR Decoupler exists in the FPGA fabric to isolate one
123 region of the FPGA from the busses while that region is
127 tristate "FPGA Region"
130 FPGA Region common code. A FPGA Region controls a FPGA Manager
131 and the FPGA Bridges associated with either a reconfigurable
132 region of an FPGA or a whole FPGA.
135 tristate "FPGA Region Device Tree Overlay Support"
138 Support for loading FPGA images by applying a Device Tree
142 tristate "FPGA Device Feature List (DFL) support"
149 to provide an extensible way of adding features for FPGA.
151 devices (e.g. FPGA Management Engine, Port and Accelerator
152 Function Unit) and their private features for target FPGA devices.
155 Gate Array (FPGA) solutions which implement Device Feature List.
159 tristate "FPGA DFL FME Driver"
162 The FPGA Management Engine (FME) is a feature device implemented
165 FPGA platform level management features. There shall be one FME
166 per DFL based FPGA device.
169 tristate "FPGA DFL FME Manager Driver"
172 Say Y to enable FPGA Manager driver for FPGA Management Engine.
175 tristate "FPGA DFL FME Bridge Driver"
178 Say Y to enable FPGA Bridge driver for FPGA Management Engine.
181 tristate "FPGA DFL FME Region Driver"
184 Say Y to enable FPGA Region driver for FPGA Management Engine.
187 tristate "FPGA DFL AFU Driver"
190 This is the driver for FPGA Accelerated Function Unit (AFU) which
192 to the FPGA infrastructure via a Port. There may be more than one
193 Port/AFU per DFL based FPGA device.
196 tristate "FPGA DFL PCIe Device Driver"
200 Field-Programmable Gate Array (FPGA) solutions which implement
203 FPGA accelerators on the FPGA DFL devices, enables system level
204 management functions such as FPGA partial reconfiguration, power
211 tristate "Xilinx ZynqMP FPGA"
214 FPGA manager driver support for Xilinx ZynqMP FPGAs.
219 endif # FPGA