Lines Matching +full:hb +full:- +full:ddr +full:- +full:ctrl

1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
16 /* DDR Ctrlr Error Registers */
35 /* DDR Ctrlr Interrupt Registers */
56 struct hb_mc_drvdata *drvdata = mci->pvt_info; in highbank_mc_err_handler()
60 status = readl(drvdata->mc_int_base + HB_DDR_ECC_INT_STATUS); in highbank_mc_err_handler()
63 err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_U_ERR_ADDR); in highbank_mc_err_handler()
67 0, 0, -1, in highbank_mc_err_handler()
68 mci->ctl_name, ""); in highbank_mc_err_handler()
71 u32 syndrome = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_STAT); in highbank_mc_err_handler()
73 err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_ADDR); in highbank_mc_err_handler()
77 0, 0, -1, in highbank_mc_err_handler()
78 mci->ctl_name, ""); in highbank_mc_err_handler()
82 writel(status, drvdata->mc_int_base + HB_DDR_ECC_INT_ACK); in highbank_mc_err_handler()
88 struct hb_mc_drvdata *pdata = mci->pvt_info; in highbank_mc_err_inject()
91 reg = readl(pdata->mc_err_base + HB_DDR_ECC_OPT); in highbank_mc_err_inject()
94 writel(reg, pdata->mc_err_base + HB_DDR_ECC_OPT); in highbank_mc_err_inject()
106 return -EINVAL; in highbank_mc_inject_ctrl()
138 { .compatible = "calxeda,hb-ddr-ctrl", .data = &hb_settings },
139 { .compatible = "calxeda,ecx-2000-ddr-ctrl", .data = &mw_settings },
158 id = of_match_device(hb_ddr_ctrl_of_match, &pdev->dev); in highbank_mc_probe()
160 return -ENODEV; in highbank_mc_probe()
171 return -ENOMEM; in highbank_mc_probe()
173 mci->pdev = &pdev->dev; in highbank_mc_probe()
174 drvdata = mci->pvt_info; in highbank_mc_probe()
177 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) in highbank_mc_probe()
178 return -ENOMEM; in highbank_mc_probe()
182 dev_err(&pdev->dev, "Unable to get mem resource\n"); in highbank_mc_probe()
183 res = -ENODEV; in highbank_mc_probe()
187 if (!devm_request_mem_region(&pdev->dev, r->start, in highbank_mc_probe()
188 resource_size(r), dev_name(&pdev->dev))) { in highbank_mc_probe()
189 dev_err(&pdev->dev, "Error while requesting mem region\n"); in highbank_mc_probe()
190 res = -EBUSY; in highbank_mc_probe()
194 base = devm_ioremap(&pdev->dev, r->start, resource_size(r)); in highbank_mc_probe()
196 dev_err(&pdev->dev, "Unable to map regs\n"); in highbank_mc_probe()
197 res = -ENOMEM; in highbank_mc_probe()
201 settings = id->data; in highbank_mc_probe()
202 drvdata->mc_err_base = base + settings->err_offset; in highbank_mc_probe()
203 drvdata->mc_int_base = base + settings->int_offset; in highbank_mc_probe()
205 control = readl(drvdata->mc_err_base + HB_DDR_ECC_OPT) & 0x3; in highbank_mc_probe()
207 dev_err(&pdev->dev, "No ECC present, or ECC disabled\n"); in highbank_mc_probe()
208 res = -ENODEV; in highbank_mc_probe()
212 mci->mtype_cap = MEM_FLAG_DDR3; in highbank_mc_probe()
213 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; in highbank_mc_probe()
214 mci->edac_cap = EDAC_FLAG_SECDED; in highbank_mc_probe()
215 mci->mod_name = pdev->dev.driver->name; in highbank_mc_probe()
216 mci->ctl_name = id->compatible; in highbank_mc_probe()
217 mci->dev_name = dev_name(&pdev->dev); in highbank_mc_probe()
218 mci->scrub_mode = SCRUB_SW_SRC; in highbank_mc_probe()
221 dimm = *mci->dimms; in highbank_mc_probe()
222 dimm->nr_pages = (~0UL >> PAGE_SHIFT) + 1; in highbank_mc_probe()
223 dimm->grain = 8; in highbank_mc_probe()
224 dimm->dtype = DEV_X8; in highbank_mc_probe()
225 dimm->mtype = MEM_DDR3; in highbank_mc_probe()
226 dimm->edac_mode = EDAC_SECDED; in highbank_mc_probe()
233 res = devm_request_irq(&pdev->dev, irq, highbank_mc_err_handler, in highbank_mc_probe()
234 0, dev_name(&pdev->dev), mci); in highbank_mc_probe()
236 dev_err(&pdev->dev, "Unable to request irq %d\n", irq); in highbank_mc_probe()
240 devres_close_group(&pdev->dev, NULL); in highbank_mc_probe()
243 edac_mc_del_mc(&pdev->dev); in highbank_mc_probe()
245 devres_release_group(&pdev->dev, NULL); in highbank_mc_probe()
254 edac_mc_del_mc(&pdev->dev); in highbank_mc_remove()