Lines Matching full:and
4 # Licensed and distributed under the GPL
13 tristate "EDAC (Error Detection And Correction) reporting"
40 levels are 0-4 (from low to high) and by default it is set to 2.
68 It should be noticed that keeping both GHES and a hardware-driven
81 Support for error detection and correction of DRAM ECC errors on
88 Recent Opterons (Family 10h and later) provide for Memory Error
90 allows the operator/user to inject Uncorrectable and Correctable
100 In addition, there are two control files, inject_read and inject_write,
101 which trigger the DRAM ECC Read and Write respectively.
107 Support for error detection and correction for Amazon's Annapurna
108 Labs Alpine chips which allow 1 bit correction and 2 bits detection.
114 Support for error detection and correction on the AMD 76x
121 Support for error detection and correction on the Intel
122 E7205, E7500, E7501 and E7505 server chipsets.
125 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
128 Support for error detection and correction on the Intel
136 Support for error detection and correction on the Intel
143 Support for error detection and correction on the Intel
144 DP82785P and E7210 server chipsets.
150 Support for error detection and correction on the Intel
157 Support for error detection and correction on the Intel
158 3000 and 3010 server chipsets.
164 Support for error detection and correction on the Intel
165 3200 and 3210 server chipsets.
171 Support for error detection and correction on the Intel
178 Support for error detection and correction on the Intel
185 Support for error detection and correction the Intel
192 Support for error detection and correction the Intel
195 and Xeon 55xx processors.
201 Support for error detection and correction on the Intel
208 Support for error detection and correction on the Radisys
215 Support for error detection and correction the Intel
222 Support for error detection and correction the Intel
229 Support for error detection and correction the Intel
236 Support for error detection and correction the Intel
237 Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
246 Support for error detection and correction the Intel
258 Support for error detection and correction the Intel
267 Support for error detection and correction on the Intel
269 first used on the Apollo Lake platform and Denverton
276 Support for error detection and correction on the Freescale
283 Support for error detection and correction on Freescale memory
290 Support for error detection and correction on the Marvell
291 MV64360 and MV64460 chipsets.
297 Support for error detection and correction on PA Semi
304 Support for error detection and correction on the
315 440SP, 440SPe, 460EX, 460GT and 460SX.
321 Support for error detection and correction on the
330 Support for error detection and correction on the
339 Support for error detection and correction on the
340 IBM CPC925 Bridge and Memory Controller, which is
348 Support for error detection and correction on the
355 Support for error detection and correction on the
362 Support for error detection and correction on the primary caches of
369 Support for error detection and correction on the
376 Support for error detection and correction on the
383 Support for error detection and correction on the
391 Support for error detection and correction on the
393 Coherent Processor Interconnect (CCPI) and L2 cache
400 Support for error detection and correction on the
408 Support for error detection and correction on the
417 Support for error detection and correction on the
425 Support for error detection and correction on the
432 Support for error detection and correction on the
439 Support for error detection and correction on the
446 Support for error detection and correction on the
453 Support for error detection and correction on the
460 Support for error detection and correction on the
467 Support for error detection and correction on the
474 Support for error detection and correction on the SiFive SoCs.
477 bool "Marvell Armada XP DDR and L2 Cache ECC"
480 Support for error correction and detection on the Marvell Aramada XP
481 DDR RAM and L2 cache controllers.
487 Support for error detection and correction on the Synopsys DDR
494 Support for error detection and correction on the
501 Support for error detection and correction on the TI SoCs.
507 Support for error detection and correction on the
510 This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs).
512 of Tag RAM and Data RAM.
514 For debugging issues having to do with stability and overall system
521 Support for error detection and correction on the Aspeed AST 2500 SoC.
530 Support for error detection and correction on the
537 Support for error detection and correction on the