Lines Matching refs:edma_shadow0_write_array
398 static inline void edma_shadow0_write_array(struct edma_cc *ecc, int offset, in edma_shadow0_write_array() function
461 edma_shadow0_write_array(ecc, SH_ICR, idx, ch_bit); in edma_setup_interrupt()
462 edma_shadow0_write_array(ecc, SH_IESR, idx, ch_bit); in edma_setup_interrupt()
464 edma_shadow0_write_array(ecc, SH_IECR, idx, ch_bit); in edma_setup_interrupt()
609 edma_shadow0_write_array(ecc, SH_ESR, idx, ch_bit); in edma_start()
618 edma_shadow0_write_array(ecc, SH_SECR, idx, ch_bit); in edma_start()
619 edma_shadow0_write_array(ecc, SH_EESR, idx, ch_bit); in edma_start()
632 edma_shadow0_write_array(ecc, SH_EECR, idx, ch_bit); in edma_stop()
633 edma_shadow0_write_array(ecc, SH_ECR, idx, ch_bit); in edma_stop()
634 edma_shadow0_write_array(ecc, SH_SECR, idx, ch_bit); in edma_stop()
638 edma_shadow0_write_array(ecc, SH_ICR, idx, ch_bit); in edma_stop()
656 edma_shadow0_write_array(echan->ecc, SH_EECR, in edma_pause()
666 edma_shadow0_write_array(echan->ecc, SH_EESR, in edma_resume()
678 edma_shadow0_write_array(ecc, SH_ESR, idx, ch_bit); in edma_trigger_channel()
693 edma_shadow0_write_array(ecc, SH_ECR, idx, ch_bit); in edma_clean_channel()
697 edma_shadow0_write_array(ecc, SH_SECR, idx, ch_bit); in edma_clean_channel()
1584 edma_shadow0_write_array(ecc, SH_ICR, bank, BIT(slot)); in dma_irq_handler()
1691 edma_shadow0_write_array(ecc, SH_SECR, j, in dma_ccerr_handler()