Lines Matching +full:imx35 +full:- +full:spdif
1 // SPDX-License-Identifier: GPL-2.0+
3 // drivers/dma/imx-sdma.c
11 // Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
26 #include <linux/dma-mapping.h>
38 #include <linux/platform_data/dma-imx-sdma.h>
39 #include <linux/platform_data/dma-imx.h>
42 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
45 #include "virt-dma.h"
129 * 0-7 Lower WML Lower watermark level
134 * 10 SPDIF If this bit is set both source
140 * 13-15 --------- MUST BE 0
141 * 16-23 Higher WML HWML
142 * 24-27 N Total number of samples after
153 * 30 --------- MUST BE 0
185 * Mode/Count of data node descriptors - IPCv2
204 * struct sdma_channel_control - Channel control Block
218 * struct sdma_state_registers - SDMA context for a channel
247 * struct sdma_context_data - sdma context specific to a channel
305 * struct sdma_desc - descriptor structor for one transfer
312 * @chn_real_count: the real count updated from bd->mode.count
331 * struct sdma_channel - housekeeping for a SDMA channel
397 * struct sdma_firmware_header - Layout of the firmware image
571 .name = "imx25-sdma",
574 .name = "imx31-sdma",
577 .name = "imx35-sdma",
580 .name = "imx51-sdma",
583 .name = "imx53-sdma",
586 .name = "imx6q-sdma",
589 .name = "imx7d-sdma",
592 .name = "imx8mq-sdma",
601 { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, },
602 { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, },
603 { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, },
604 { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, },
605 { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
606 { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
607 { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, },
608 { .compatible = "fsl,imx8mq-sdma", .data = &sdma_imx8mq, },
614 #define SDMA_H_CONFIG_RTD_PINS BIT(11) /* indicates if Real-Time Debug pins are enabled */
620 u32 chnenbl0 = sdma->drvdata->chnenbl0; in chnenbl_ofs()
627 struct sdma_engine *sdma = sdmac->sdma; in sdma_config_ownership()
628 int channel = sdmac->channel; in sdma_config_ownership()
632 return -EINVAL; in sdma_config_ownership()
634 evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR); in sdma_config_ownership()
635 mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR); in sdma_config_ownership()
636 dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR); in sdma_config_ownership()
653 writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR); in sdma_config_ownership()
654 writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR); in sdma_config_ownership()
655 writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR); in sdma_config_ownership()
662 writel(BIT(channel), sdma->regs + SDMA_H_START); in sdma_enable_channel()
666 * sdma_run_channel0 - run a channel and wait till it's done
675 ret = readl_relaxed_poll_timeout_atomic(sdma->regs + SDMA_H_STATSTOP, in sdma_run_channel0()
678 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n"); in sdma_run_channel0()
681 reg = readl(sdma->regs + SDMA_H_CONFIG); in sdma_run_channel0()
684 writel_relaxed(reg, sdma->regs + SDMA_H_CONFIG); in sdma_run_channel0()
693 struct sdma_buffer_descriptor *bd0 = sdma->bd0; in sdma_load_script()
699 buf_virt = dma_alloc_coherent(sdma->dev, size, &buf_phys, GFP_KERNEL); in sdma_load_script()
701 return -ENOMEM; in sdma_load_script()
704 spin_lock_irqsave(&sdma->channel_0_lock, flags); in sdma_load_script()
706 bd0->mode.command = C0_SETPM; in sdma_load_script()
707 bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD; in sdma_load_script()
708 bd0->mode.count = size / 2; in sdma_load_script()
709 bd0->buffer_addr = buf_phys; in sdma_load_script()
710 bd0->ext_buffer_addr = address; in sdma_load_script()
716 spin_unlock_irqrestore(&sdma->channel_0_lock, flags); in sdma_load_script()
718 dma_free_coherent(sdma->dev, size, buf_virt, buf_phys); in sdma_load_script()
725 struct sdma_engine *sdma = sdmac->sdma; in sdma_event_enable()
726 int channel = sdmac->channel; in sdma_event_enable()
730 val = readl_relaxed(sdma->regs + chnenbl); in sdma_event_enable()
732 writel_relaxed(val, sdma->regs + chnenbl); in sdma_event_enable()
737 struct sdma_engine *sdma = sdmac->sdma; in sdma_event_disable()
738 int channel = sdmac->channel; in sdma_event_disable()
742 val = readl_relaxed(sdma->regs + chnenbl); in sdma_event_disable()
744 writel_relaxed(val, sdma->regs + chnenbl); in sdma_event_disable()
754 struct virt_dma_desc *vd = vchan_next_desc(&sdmac->vc); in sdma_start_desc()
756 struct sdma_engine *sdma = sdmac->sdma; in sdma_start_desc()
757 int channel = sdmac->channel; in sdma_start_desc()
760 sdmac->desc = NULL; in sdma_start_desc()
763 sdmac->desc = desc = to_sdma_desc(&vd->tx); in sdma_start_desc()
765 list_del(&vd->node); in sdma_start_desc()
767 sdma->channel_control[channel].base_bd_ptr = desc->bd_phys; in sdma_start_desc()
768 sdma->channel_control[channel].current_bd_ptr = desc->bd_phys; in sdma_start_desc()
769 sdma_enable_channel(sdma, sdmac->channel); in sdma_start_desc()
776 enum dma_status old_status = sdmac->status; in sdma_update_channel_loop()
779 * loop mode. Iterate over descriptors, re-setup them and in sdma_update_channel_loop()
782 while (sdmac->desc) { in sdma_update_channel_loop()
783 struct sdma_desc *desc = sdmac->desc; in sdma_update_channel_loop()
785 bd = &desc->bd[desc->buf_tail]; in sdma_update_channel_loop()
787 if (bd->mode.status & BD_DONE) in sdma_update_channel_loop()
790 if (bd->mode.status & BD_RROR) { in sdma_update_channel_loop()
791 bd->mode.status &= ~BD_RROR; in sdma_update_channel_loop()
792 sdmac->status = DMA_ERROR; in sdma_update_channel_loop()
793 error = -EIO; in sdma_update_channel_loop()
797 * We use bd->mode.count to calculate the residue, since contains in sdma_update_channel_loop()
801 desc->chn_real_count = bd->mode.count; in sdma_update_channel_loop()
802 bd->mode.status |= BD_DONE; in sdma_update_channel_loop()
803 bd->mode.count = desc->period_len; in sdma_update_channel_loop()
804 desc->buf_ptail = desc->buf_tail; in sdma_update_channel_loop()
805 desc->buf_tail = (desc->buf_tail + 1) % desc->num_bd; in sdma_update_channel_loop()
813 spin_unlock(&sdmac->vc.lock); in sdma_update_channel_loop()
814 dmaengine_desc_get_callback_invoke(&desc->vd.tx, NULL); in sdma_update_channel_loop()
815 spin_lock(&sdmac->vc.lock); in sdma_update_channel_loop()
818 sdmac->status = old_status; in sdma_update_channel_loop()
828 sdmac->desc->chn_real_count = 0; in mxc_sdma_handle_channel_normal()
833 for (i = 0; i < sdmac->desc->num_bd; i++) { in mxc_sdma_handle_channel_normal()
834 bd = &sdmac->desc->bd[i]; in mxc_sdma_handle_channel_normal()
836 if (bd->mode.status & (BD_DONE | BD_RROR)) in mxc_sdma_handle_channel_normal()
837 error = -EIO; in mxc_sdma_handle_channel_normal()
838 sdmac->desc->chn_real_count += bd->mode.count; in mxc_sdma_handle_channel_normal()
842 sdmac->status = DMA_ERROR; in mxc_sdma_handle_channel_normal()
844 sdmac->status = DMA_COMPLETE; in mxc_sdma_handle_channel_normal()
852 stat = readl_relaxed(sdma->regs + SDMA_H_INTR); in sdma_int_handler()
853 writel_relaxed(stat, sdma->regs + SDMA_H_INTR); in sdma_int_handler()
858 int channel = fls(stat) - 1; in sdma_int_handler()
859 struct sdma_channel *sdmac = &sdma->channel[channel]; in sdma_int_handler()
862 spin_lock(&sdmac->vc.lock); in sdma_int_handler()
863 desc = sdmac->desc; in sdma_int_handler()
865 if (sdmac->flags & IMX_DMA_SG_LOOP) { in sdma_int_handler()
869 vchan_cookie_complete(&desc->vd); in sdma_int_handler()
874 spin_unlock(&sdmac->vc.lock); in sdma_int_handler()
887 struct sdma_engine *sdma = sdmac->sdma; in sdma_get_pc()
891 * two peripherals or memory-to-memory transfers in sdma_get_pc()
895 sdmac->pc_from_device = 0; in sdma_get_pc()
896 sdmac->pc_to_device = 0; in sdma_get_pc()
897 sdmac->device_to_device = 0; in sdma_get_pc()
898 sdmac->pc_to_pc = 0; in sdma_get_pc()
902 emi_2_emi = sdma->script_addrs->ap_2_ap_addr; in sdma_get_pc()
905 emi_2_per = sdma->script_addrs->bp_2_ap_addr; in sdma_get_pc()
906 per_2_emi = sdma->script_addrs->ap_2_bp_addr; in sdma_get_pc()
909 per_2_emi = sdma->script_addrs->firi_2_mcu_addr; in sdma_get_pc()
910 emi_2_per = sdma->script_addrs->mcu_2_firi_addr; in sdma_get_pc()
913 per_2_emi = sdma->script_addrs->uart_2_mcu_addr; in sdma_get_pc()
914 emi_2_per = sdma->script_addrs->mcu_2_app_addr; in sdma_get_pc()
917 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr; in sdma_get_pc()
918 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; in sdma_get_pc()
921 per_2_emi = sdma->script_addrs->ata_2_mcu_addr; in sdma_get_pc()
922 emi_2_per = sdma->script_addrs->mcu_2_ata_addr; in sdma_get_pc()
928 per_2_emi = sdma->script_addrs->app_2_mcu_addr; in sdma_get_pc()
929 emi_2_per = sdma->script_addrs->mcu_2_app_addr; in sdma_get_pc()
932 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr; in sdma_get_pc()
933 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr; in sdma_get_pc()
941 per_2_emi = sdma->script_addrs->shp_2_mcu_addr; in sdma_get_pc()
942 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; in sdma_get_pc()
945 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr; in sdma_get_pc()
946 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr; in sdma_get_pc()
947 per_2_per = sdma->script_addrs->per_2_per_addr; in sdma_get_pc()
950 per_2_emi = sdma->script_addrs->shp_2_mcu_addr; in sdma_get_pc()
951 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; in sdma_get_pc()
952 per_2_per = sdma->script_addrs->per_2_per_addr; in sdma_get_pc()
955 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr; in sdma_get_pc()
956 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr; in sdma_get_pc()
959 per_2_emi = sdma->script_addrs->dptc_dvfs_addr; in sdma_get_pc()
962 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr; in sdma_get_pc()
963 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr; in sdma_get_pc()
966 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr; in sdma_get_pc()
972 sdmac->pc_from_device = per_2_emi; in sdma_get_pc()
973 sdmac->pc_to_device = emi_2_per; in sdma_get_pc()
974 sdmac->device_to_device = per_2_per; in sdma_get_pc()
975 sdmac->pc_to_pc = emi_2_emi; in sdma_get_pc()
980 struct sdma_engine *sdma = sdmac->sdma; in sdma_load_context()
981 int channel = sdmac->channel; in sdma_load_context()
983 struct sdma_context_data *context = sdma->context; in sdma_load_context()
984 struct sdma_buffer_descriptor *bd0 = sdma->bd0; in sdma_load_context()
988 if (sdmac->context_loaded) in sdma_load_context()
991 if (sdmac->direction == DMA_DEV_TO_MEM) in sdma_load_context()
992 load_address = sdmac->pc_from_device; in sdma_load_context()
993 else if (sdmac->direction == DMA_DEV_TO_DEV) in sdma_load_context()
994 load_address = sdmac->device_to_device; in sdma_load_context()
995 else if (sdmac->direction == DMA_MEM_TO_MEM) in sdma_load_context()
996 load_address = sdmac->pc_to_pc; in sdma_load_context()
998 load_address = sdmac->pc_to_device; in sdma_load_context()
1003 dev_dbg(sdma->dev, "load_address = %d\n", load_address); in sdma_load_context()
1004 dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level); in sdma_load_context()
1005 dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr); in sdma_load_context()
1006 dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr); in sdma_load_context()
1007 dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]); in sdma_load_context()
1008 dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]); in sdma_load_context()
1010 spin_lock_irqsave(&sdma->channel_0_lock, flags); in sdma_load_context()
1013 context->channel_state.pc = load_address; in sdma_load_context()
1018 context->gReg[0] = sdmac->event_mask[1]; in sdma_load_context()
1019 context->gReg[1] = sdmac->event_mask[0]; in sdma_load_context()
1020 context->gReg[2] = sdmac->per_addr; in sdma_load_context()
1021 context->gReg[6] = sdmac->shp_addr; in sdma_load_context()
1022 context->gReg[7] = sdmac->watermark_level; in sdma_load_context()
1024 bd0->mode.command = C0_SETDM; in sdma_load_context()
1025 bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD; in sdma_load_context()
1026 bd0->mode.count = sizeof(*context) / 4; in sdma_load_context()
1027 bd0->buffer_addr = sdma->context_phys; in sdma_load_context()
1028 bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel; in sdma_load_context()
1031 spin_unlock_irqrestore(&sdma->channel_0_lock, flags); in sdma_load_context()
1033 sdmac->context_loaded = true; in sdma_load_context()
1046 struct sdma_engine *sdma = sdmac->sdma; in sdma_disable_channel()
1047 int channel = sdmac->channel; in sdma_disable_channel()
1049 writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP); in sdma_disable_channel()
1050 sdmac->status = DMA_ERROR; in sdma_disable_channel()
1069 spin_lock_irqsave(&sdmac->vc.lock, flags); in sdma_channel_terminate_work()
1070 vchan_get_all_descriptors(&sdmac->vc, &head); in sdma_channel_terminate_work()
1071 spin_unlock_irqrestore(&sdmac->vc.lock, flags); in sdma_channel_terminate_work()
1072 vchan_dma_desc_free_list(&sdmac->vc, &head); in sdma_channel_terminate_work()
1073 sdmac->context_loaded = false; in sdma_channel_terminate_work()
1081 spin_lock_irqsave(&sdmac->vc.lock, flags); in sdma_terminate_all()
1085 if (sdmac->desc) { in sdma_terminate_all()
1086 vchan_terminate_vdesc(&sdmac->desc->vd); in sdma_terminate_all()
1087 sdmac->desc = NULL; in sdma_terminate_all()
1088 schedule_work(&sdmac->terminate_worker); in sdma_terminate_all()
1091 spin_unlock_irqrestore(&sdmac->vc.lock, flags); in sdma_terminate_all()
1100 vchan_synchronize(&sdmac->vc); in sdma_channel_synchronize()
1102 flush_work(&sdmac->terminate_worker); in sdma_channel_synchronize()
1107 struct sdma_engine *sdma = sdmac->sdma; in sdma_set_watermarklevel_for_p2p()
1109 int lwml = sdmac->watermark_level & SDMA_WATERMARK_LEVEL_LWML; in sdma_set_watermarklevel_for_p2p()
1110 int hwml = (sdmac->watermark_level & SDMA_WATERMARK_LEVEL_HWML) >> 16; in sdma_set_watermarklevel_for_p2p()
1112 set_bit(sdmac->event_id0 % 32, &sdmac->event_mask[1]); in sdma_set_watermarklevel_for_p2p()
1113 set_bit(sdmac->event_id1 % 32, &sdmac->event_mask[0]); in sdma_set_watermarklevel_for_p2p()
1115 if (sdmac->event_id0 > 31) in sdma_set_watermarklevel_for_p2p()
1116 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_LWE; in sdma_set_watermarklevel_for_p2p()
1118 if (sdmac->event_id1 > 31) in sdma_set_watermarklevel_for_p2p()
1119 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_HWE; in sdma_set_watermarklevel_for_p2p()
1127 sdmac->watermark_level &= ~(SDMA_WATERMARK_LEVEL_LWML | in sdma_set_watermarklevel_for_p2p()
1129 sdmac->watermark_level |= hwml; in sdma_set_watermarklevel_for_p2p()
1130 sdmac->watermark_level |= lwml << 16; in sdma_set_watermarklevel_for_p2p()
1131 swap(sdmac->event_mask[0], sdmac->event_mask[1]); in sdma_set_watermarklevel_for_p2p()
1134 if (sdmac->per_address2 >= sdma->spba_start_addr && in sdma_set_watermarklevel_for_p2p()
1135 sdmac->per_address2 <= sdma->spba_end_addr) in sdma_set_watermarklevel_for_p2p()
1136 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SP; in sdma_set_watermarklevel_for_p2p()
1138 if (sdmac->per_address >= sdma->spba_start_addr && in sdma_set_watermarklevel_for_p2p()
1139 sdmac->per_address <= sdma->spba_end_addr) in sdma_set_watermarklevel_for_p2p()
1140 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP; in sdma_set_watermarklevel_for_p2p()
1142 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT; in sdma_set_watermarklevel_for_p2p()
1152 sdmac->event_mask[0] = 0; in sdma_config_channel()
1153 sdmac->event_mask[1] = 0; in sdma_config_channel()
1154 sdmac->shp_addr = 0; in sdma_config_channel()
1155 sdmac->per_addr = 0; in sdma_config_channel()
1157 switch (sdmac->peripheral_type) { in sdma_config_channel()
1169 sdma_get_pc(sdmac, sdmac->peripheral_type); in sdma_config_channel()
1171 if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) && in sdma_config_channel()
1172 (sdmac->peripheral_type != IMX_DMATYPE_DSP)) { in sdma_config_channel()
1174 if (sdmac->event_id1) { in sdma_config_channel()
1175 if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP || in sdma_config_channel()
1176 sdmac->peripheral_type == IMX_DMATYPE_ASRC) in sdma_config_channel()
1179 __set_bit(sdmac->event_id0, sdmac->event_mask); in sdma_config_channel()
1182 sdmac->shp_addr = sdmac->per_address; in sdma_config_channel()
1183 sdmac->per_addr = sdmac->per_address2; in sdma_config_channel()
1185 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */ in sdma_config_channel()
1196 struct sdma_engine *sdma = sdmac->sdma; in sdma_set_channel_priority()
1197 int channel = sdmac->channel; in sdma_set_channel_priority()
1201 return -EINVAL; in sdma_set_channel_priority()
1204 writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel); in sdma_set_channel_priority()
1211 int ret = -EBUSY; in sdma_request_channel0()
1213 sdma->bd0 = dma_alloc_coherent(sdma->dev, PAGE_SIZE, &sdma->bd0_phys, in sdma_request_channel0()
1215 if (!sdma->bd0) { in sdma_request_channel0()
1216 ret = -ENOMEM; in sdma_request_channel0()
1220 sdma->channel_control[0].base_bd_ptr = sdma->bd0_phys; in sdma_request_channel0()
1221 sdma->channel_control[0].current_bd_ptr = sdma->bd0_phys; in sdma_request_channel0()
1223 sdma_set_channel_priority(&sdma->channel[0], MXC_SDMA_DEFAULT_PRIORITY); in sdma_request_channel0()
1233 u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor); in sdma_alloc_bd()
1236 desc->bd = dma_alloc_coherent(desc->sdmac->sdma->dev, bd_size, in sdma_alloc_bd()
1237 &desc->bd_phys, GFP_NOWAIT); in sdma_alloc_bd()
1238 if (!desc->bd) { in sdma_alloc_bd()
1239 ret = -ENOMEM; in sdma_alloc_bd()
1248 u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor); in sdma_free_bd()
1250 dma_free_coherent(desc->sdmac->sdma->dev, bd_size, desc->bd, in sdma_free_bd()
1251 desc->bd_phys); in sdma_free_bd()
1265 struct imx_dma_data *data = chan->private; in sdma_alloc_chan_resources()
1270 * MEMCPY may never setup chan->private by filter function such as in sdma_alloc_chan_resources()
1272 * Please note in any other slave case, you have to setup chan->private in sdma_alloc_chan_resources()
1279 dev_dbg(sdmac->sdma->dev, "MEMCPY in case?\n"); in sdma_alloc_chan_resources()
1289 switch (data->priority) { in sdma_alloc_chan_resources()
1302 sdmac->peripheral_type = data->peripheral_type; in sdma_alloc_chan_resources()
1303 sdmac->event_id0 = data->dma_request; in sdma_alloc_chan_resources()
1304 sdmac->event_id1 = data->dma_request2; in sdma_alloc_chan_resources()
1306 ret = clk_enable(sdmac->sdma->clk_ipg); in sdma_alloc_chan_resources()
1309 ret = clk_enable(sdmac->sdma->clk_ahb); in sdma_alloc_chan_resources()
1320 clk_disable(sdmac->sdma->clk_ahb); in sdma_alloc_chan_resources()
1322 clk_disable(sdmac->sdma->clk_ipg); in sdma_alloc_chan_resources()
1329 struct sdma_engine *sdma = sdmac->sdma; in sdma_free_chan_resources()
1335 sdma_event_disable(sdmac, sdmac->event_id0); in sdma_free_chan_resources()
1336 if (sdmac->event_id1) in sdma_free_chan_resources()
1337 sdma_event_disable(sdmac, sdmac->event_id1); in sdma_free_chan_resources()
1339 sdmac->event_id0 = 0; in sdma_free_chan_resources()
1340 sdmac->event_id1 = 0; in sdma_free_chan_resources()
1341 sdmac->context_loaded = false; in sdma_free_chan_resources()
1345 clk_disable(sdma->clk_ipg); in sdma_free_chan_resources()
1346 clk_disable(sdma->clk_ahb); in sdma_free_chan_resources()
1358 sdmac->status = DMA_IN_PROGRESS; in sdma_transfer_init()
1359 sdmac->direction = direction; in sdma_transfer_init()
1360 sdmac->flags = 0; in sdma_transfer_init()
1362 desc->chn_count = 0; in sdma_transfer_init()
1363 desc->chn_real_count = 0; in sdma_transfer_init()
1364 desc->buf_tail = 0; in sdma_transfer_init()
1365 desc->buf_ptail = 0; in sdma_transfer_init()
1366 desc->sdmac = sdmac; in sdma_transfer_init()
1367 desc->num_bd = bds; in sdma_transfer_init()
1392 struct sdma_engine *sdma = sdmac->sdma; in sdma_prep_memcpy()
1393 int channel = sdmac->channel; in sdma_prep_memcpy()
1402 dev_dbg(sdma->dev, "memcpy: %pad->%pad, len=%zu, channel=%d.\n", in sdma_prep_memcpy()
1412 bd = &desc->bd[i]; in sdma_prep_memcpy()
1413 bd->buffer_addr = dma_src; in sdma_prep_memcpy()
1414 bd->ext_buffer_addr = dma_dst; in sdma_prep_memcpy()
1415 bd->mode.count = count; in sdma_prep_memcpy()
1416 desc->chn_count += count; in sdma_prep_memcpy()
1417 bd->mode.command = 0; in sdma_prep_memcpy()
1421 len -= count; in sdma_prep_memcpy()
1432 dev_dbg(sdma->dev, "entry %d: count: %zd dma: 0x%x %s%s\n", in sdma_prep_memcpy()
1433 i, count, bd->buffer_addr, in sdma_prep_memcpy()
1437 bd->mode.status = param; in sdma_prep_memcpy()
1440 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); in sdma_prep_memcpy()
1449 struct sdma_engine *sdma = sdmac->sdma; in sdma_prep_slave_sg()
1451 int channel = sdmac->channel; in sdma_prep_slave_sg()
1455 sdma_config_write(chan, &sdmac->slave_config, direction); in sdma_prep_slave_sg()
1461 dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n", in sdma_prep_slave_sg()
1465 struct sdma_buffer_descriptor *bd = &desc->bd[i]; in sdma_prep_slave_sg()
1468 bd->buffer_addr = sg->dma_address; in sdma_prep_slave_sg()
1473 dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n", in sdma_prep_slave_sg()
1478 bd->mode.count = count; in sdma_prep_slave_sg()
1479 desc->chn_count += count; in sdma_prep_slave_sg()
1481 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) in sdma_prep_slave_sg()
1484 switch (sdmac->word_size) { in sdma_prep_slave_sg()
1486 bd->mode.command = 0; in sdma_prep_slave_sg()
1487 if (count & 3 || sg->dma_address & 3) in sdma_prep_slave_sg()
1491 bd->mode.command = 2; in sdma_prep_slave_sg()
1492 if (count & 1 || sg->dma_address & 1) in sdma_prep_slave_sg()
1496 bd->mode.command = 1; in sdma_prep_slave_sg()
1510 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n", in sdma_prep_slave_sg()
1511 i, count, (u64)sg->dma_address, in sdma_prep_slave_sg()
1515 bd->mode.status = param; in sdma_prep_slave_sg()
1518 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); in sdma_prep_slave_sg()
1523 sdmac->status = DMA_ERROR; in sdma_prep_slave_sg()
1533 struct sdma_engine *sdma = sdmac->sdma; in sdma_prep_dma_cyclic()
1535 int channel = sdmac->channel; in sdma_prep_dma_cyclic()
1539 dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel); in sdma_prep_dma_cyclic()
1541 sdma_config_write(chan, &sdmac->slave_config, direction); in sdma_prep_dma_cyclic()
1547 desc->period_len = period_len; in sdma_prep_dma_cyclic()
1549 sdmac->flags |= IMX_DMA_SG_LOOP; in sdma_prep_dma_cyclic()
1552 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %zu > %d\n", in sdma_prep_dma_cyclic()
1558 struct sdma_buffer_descriptor *bd = &desc->bd[i]; in sdma_prep_dma_cyclic()
1561 bd->buffer_addr = dma_addr; in sdma_prep_dma_cyclic()
1563 bd->mode.count = period_len; in sdma_prep_dma_cyclic()
1565 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) in sdma_prep_dma_cyclic()
1567 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES) in sdma_prep_dma_cyclic()
1568 bd->mode.command = 0; in sdma_prep_dma_cyclic()
1570 bd->mode.command = sdmac->word_size; in sdma_prep_dma_cyclic()
1576 dev_dbg(sdma->dev, "entry %d: count: %zu dma: %#llx %s%s\n", in sdma_prep_dma_cyclic()
1581 bd->mode.status = param; in sdma_prep_dma_cyclic()
1589 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); in sdma_prep_dma_cyclic()
1594 sdmac->status = DMA_ERROR; in sdma_prep_dma_cyclic()
1605 sdmac->per_address = dmaengine_cfg->src_addr; in sdma_config_write()
1606 sdmac->watermark_level = dmaengine_cfg->src_maxburst * in sdma_config_write()
1607 dmaengine_cfg->src_addr_width; in sdma_config_write()
1608 sdmac->word_size = dmaengine_cfg->src_addr_width; in sdma_config_write()
1610 sdmac->per_address2 = dmaengine_cfg->src_addr; in sdma_config_write()
1611 sdmac->per_address = dmaengine_cfg->dst_addr; in sdma_config_write()
1612 sdmac->watermark_level = dmaengine_cfg->src_maxburst & in sdma_config_write()
1614 sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) & in sdma_config_write()
1616 sdmac->word_size = dmaengine_cfg->dst_addr_width; in sdma_config_write()
1618 sdmac->per_address = dmaengine_cfg->dst_addr; in sdma_config_write()
1619 sdmac->watermark_level = dmaengine_cfg->dst_maxburst * in sdma_config_write()
1620 dmaengine_cfg->dst_addr_width; in sdma_config_write()
1621 sdmac->word_size = dmaengine_cfg->dst_addr_width; in sdma_config_write()
1623 sdmac->direction = direction; in sdma_config_write()
1632 memcpy(&sdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg)); in sdma_config()
1635 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events) in sdma_config()
1636 return -EINVAL; in sdma_config()
1637 sdma_event_enable(sdmac, sdmac->event_id0); in sdma_config()
1639 if (sdmac->event_id1) { in sdma_config()
1640 if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events) in sdma_config()
1641 return -EINVAL; in sdma_config()
1642 sdma_event_enable(sdmac, sdmac->event_id1); in sdma_config()
1663 spin_lock_irqsave(&sdmac->vc.lock, flags); in sdma_tx_status()
1665 vd = vchan_find_desc(&sdmac->vc, cookie); in sdma_tx_status()
1667 desc = to_sdma_desc(&vd->tx); in sdma_tx_status()
1668 else if (sdmac->desc && sdmac->desc->vd.tx.cookie == cookie) in sdma_tx_status()
1669 desc = sdmac->desc; in sdma_tx_status()
1672 if (sdmac->flags & IMX_DMA_SG_LOOP) in sdma_tx_status()
1673 residue = (desc->num_bd - desc->buf_ptail) * in sdma_tx_status()
1674 desc->period_len - desc->chn_real_count; in sdma_tx_status()
1676 residue = desc->chn_count - desc->chn_real_count; in sdma_tx_status()
1681 spin_unlock_irqrestore(&sdmac->vc.lock, flags); in sdma_tx_status()
1683 dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie, in sdma_tx_status()
1686 return sdmac->status; in sdma_tx_status()
1694 spin_lock_irqsave(&sdmac->vc.lock, flags); in sdma_issue_pending()
1695 if (vchan_issue_pending(&sdmac->vc) && !sdmac->desc) in sdma_issue_pending()
1697 spin_unlock_irqrestore(&sdmac->vc.lock, flags); in sdma_issue_pending()
1709 s32 *saddr_arr = (u32 *)sdma->script_addrs; in sdma_add_scripts()
1713 if (!sdma->script_number) in sdma_add_scripts()
1714 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; in sdma_add_scripts()
1716 if (sdma->script_number > sizeof(struct sdma_script_start_addrs) in sdma_add_scripts()
1718 dev_err(sdma->dev, in sdma_add_scripts()
1720 sdma->script_number); in sdma_add_scripts()
1724 for (i = 0; i < sdma->script_number; i++) in sdma_add_scripts()
1737 dev_info(sdma->dev, "external firmware not found, using ROM firmware\n"); in sdma_load_firmware()
1742 if (fw->size < sizeof(*header)) in sdma_load_firmware()
1745 header = (struct sdma_firmware_header *)fw->data; in sdma_load_firmware()
1747 if (header->magic != SDMA_FIRMWARE_MAGIC) in sdma_load_firmware()
1749 if (header->ram_code_start + header->ram_code_size > fw->size) in sdma_load_firmware()
1751 switch (header->version_major) { in sdma_load_firmware()
1753 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; in sdma_load_firmware()
1756 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2; in sdma_load_firmware()
1759 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3; in sdma_load_firmware()
1762 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4; in sdma_load_firmware()
1765 dev_err(sdma->dev, "unknown firmware version\n"); in sdma_load_firmware()
1769 addr = (void *)header + header->script_addrs_start; in sdma_load_firmware()
1770 ram_code = (void *)header + header->ram_code_start; in sdma_load_firmware()
1772 clk_enable(sdma->clk_ipg); in sdma_load_firmware()
1773 clk_enable(sdma->clk_ahb); in sdma_load_firmware()
1776 header->ram_code_size, in sdma_load_firmware()
1777 addr->ram_code_start_addr); in sdma_load_firmware()
1778 clk_disable(sdma->clk_ipg); in sdma_load_firmware()
1779 clk_disable(sdma->clk_ahb); in sdma_load_firmware()
1783 dev_info(sdma->dev, "loaded firmware %d.%d\n", in sdma_load_firmware()
1784 header->version_major, in sdma_load_firmware()
1785 header->version_minor); in sdma_load_firmware()
1795 struct device_node *np = sdma->dev->of_node; in sdma_event_remap()
1799 char propname[] = "fsl,sdma-event-remap"; in sdma_event_remap()
1807 num_map = event_remap ? (event_remap->length / sizeof(u32)) : 0; in sdma_event_remap()
1809 dev_dbg(sdma->dev, "no event needs to be remapped\n"); in sdma_event_remap()
1812 dev_err(sdma->dev, "the property %s must modulo %d\n", in sdma_event_remap()
1814 ret = -EINVAL; in sdma_event_remap()
1820 dev_err(sdma->dev, "failed to get gpr regmap\n"); in sdma_event_remap()
1828 dev_err(sdma->dev, "failed to read property %s index %d\n", in sdma_event_remap()
1835 dev_err(sdma->dev, "failed to read property %s index %d\n", in sdma_event_remap()
1842 dev_err(sdma->dev, "failed to read property %s index %d\n", in sdma_event_remap()
1863 FW_ACTION_HOTPLUG, fw_name, sdma->dev, in sdma_get_firmware()
1874 ret = clk_enable(sdma->clk_ipg); in sdma_init()
1877 ret = clk_enable(sdma->clk_ahb); in sdma_init()
1881 if (sdma->drvdata->check_ratio && in sdma_init()
1882 (clk_get_rate(sdma->clk_ahb) == clk_get_rate(sdma->clk_ipg))) in sdma_init()
1883 sdma->clk_ratio = 1; in sdma_init()
1886 writel_relaxed(0, sdma->regs + SDMA_H_C0PTR); in sdma_init()
1888 sdma->channel_control = dma_alloc_coherent(sdma->dev, in sdma_init()
1893 if (!sdma->channel_control) { in sdma_init()
1894 ret = -ENOMEM; in sdma_init()
1898 sdma->context = (void *)sdma->channel_control + in sdma_init()
1900 sdma->context_phys = ccb_phys + in sdma_init()
1904 for (i = 0; i < sdma->drvdata->num_events; i++) in sdma_init()
1905 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i)); in sdma_init()
1909 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4); in sdma_init()
1915 sdma_config_ownership(&sdma->channel[0], false, true, false); in sdma_init()
1918 writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR); in sdma_init()
1921 if (sdma->clk_ratio) in sdma_init()
1922 writel_relaxed(SDMA_H_CONFIG_ACR, sdma->regs + SDMA_H_CONFIG); in sdma_init()
1924 writel_relaxed(0, sdma->regs + SDMA_H_CONFIG); in sdma_init()
1926 writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR); in sdma_init()
1929 sdma_set_channel_priority(&sdma->channel[0], 7); in sdma_init()
1931 clk_disable(sdma->clk_ipg); in sdma_init()
1932 clk_disable(sdma->clk_ahb); in sdma_init()
1937 clk_disable(sdma->clk_ahb); in sdma_init()
1939 clk_disable(sdma->clk_ipg); in sdma_init()
1940 dev_err(sdma->dev, "initialisation failed with %d\n", ret); in sdma_init()
1952 sdmac->data = *data; in sdma_filter_fn()
1953 chan->private = &sdmac->data; in sdma_filter_fn()
1961 struct sdma_engine *sdma = ofdma->of_dma_data; in sdma_xlate()
1962 dma_cap_mask_t mask = sdma->dma_device.cap_mask; in sdma_xlate()
1965 if (dma_spec->args_count != 3) in sdma_xlate()
1968 data.dma_request = dma_spec->args[0]; in sdma_xlate()
1969 data.peripheral_type = dma_spec->args[1]; in sdma_xlate()
1970 data.priority = dma_spec->args[2]; in sdma_xlate()
1974 * chan->private will point to the imx_dma_data, and in in sdma_xlate()
1976 * be set to sdmac->event_id1. in sdma_xlate()
1981 ofdma->of_node); in sdma_xlate()
1987 of_match_device(sdma_dt_ids, &pdev->dev); in sdma_probe()
1988 struct device_node *np = pdev->dev.of_node; in sdma_probe()
1995 struct sdma_platform_data *pdata = dev_get_platdata(&pdev->dev); in sdma_probe()
2002 drvdata = of_id->data; in sdma_probe()
2003 else if (pdev->id_entry) in sdma_probe()
2004 drvdata = (void *)pdev->id_entry->driver_data; in sdma_probe()
2007 dev_err(&pdev->dev, "unable to find driver data\n"); in sdma_probe()
2008 return -EINVAL; in sdma_probe()
2011 ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); in sdma_probe()
2015 sdma = devm_kzalloc(&pdev->dev, sizeof(*sdma), GFP_KERNEL); in sdma_probe()
2017 return -ENOMEM; in sdma_probe()
2019 spin_lock_init(&sdma->channel_0_lock); in sdma_probe()
2021 sdma->dev = &pdev->dev; in sdma_probe()
2022 sdma->drvdata = drvdata; in sdma_probe()
2029 sdma->regs = devm_ioremap_resource(&pdev->dev, iores); in sdma_probe()
2030 if (IS_ERR(sdma->regs)) in sdma_probe()
2031 return PTR_ERR(sdma->regs); in sdma_probe()
2033 sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in sdma_probe()
2034 if (IS_ERR(sdma->clk_ipg)) in sdma_probe()
2035 return PTR_ERR(sdma->clk_ipg); in sdma_probe()
2037 sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); in sdma_probe()
2038 if (IS_ERR(sdma->clk_ahb)) in sdma_probe()
2039 return PTR_ERR(sdma->clk_ahb); in sdma_probe()
2041 ret = clk_prepare(sdma->clk_ipg); in sdma_probe()
2045 ret = clk_prepare(sdma->clk_ahb); in sdma_probe()
2049 ret = devm_request_irq(&pdev->dev, irq, sdma_int_handler, 0, "sdma", in sdma_probe()
2054 sdma->irq = irq; in sdma_probe()
2056 sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL); in sdma_probe()
2057 if (!sdma->script_addrs) { in sdma_probe()
2058 ret = -ENOMEM; in sdma_probe()
2063 saddr_arr = (s32 *)sdma->script_addrs; in sdma_probe()
2064 for (i = 0; i < sizeof(*sdma->script_addrs) / sizeof(s32); i++) in sdma_probe()
2065 saddr_arr[i] = -EINVAL; in sdma_probe()
2067 dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask); in sdma_probe()
2068 dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask); in sdma_probe()
2069 dma_cap_set(DMA_MEMCPY, sdma->dma_device.cap_mask); in sdma_probe()
2071 INIT_LIST_HEAD(&sdma->dma_device.channels); in sdma_probe()
2074 struct sdma_channel *sdmac = &sdma->channel[i]; in sdma_probe()
2076 sdmac->sdma = sdma; in sdma_probe()
2078 sdmac->channel = i; in sdma_probe()
2079 sdmac->vc.desc_free = sdma_desc_free; in sdma_probe()
2080 INIT_WORK(&sdmac->terminate_worker, in sdma_probe()
2088 vchan_init(&sdmac->vc, &sdma->dma_device); in sdma_probe()
2099 if (sdma->drvdata->script_addrs) in sdma_probe()
2100 sdma_add_scripts(sdma, sdma->drvdata->script_addrs); in sdma_probe()
2101 if (pdata && pdata->script_addrs) in sdma_probe()
2102 sdma_add_scripts(sdma, pdata->script_addrs); in sdma_probe()
2104 sdma->dma_device.dev = &pdev->dev; in sdma_probe()
2106 sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources; in sdma_probe()
2107 sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources; in sdma_probe()
2108 sdma->dma_device.device_tx_status = sdma_tx_status; in sdma_probe()
2109 sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg; in sdma_probe()
2110 sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic; in sdma_probe()
2111 sdma->dma_device.device_config = sdma_config; in sdma_probe()
2112 sdma->dma_device.device_terminate_all = sdma_terminate_all; in sdma_probe()
2113 sdma->dma_device.device_synchronize = sdma_channel_synchronize; in sdma_probe()
2114 sdma->dma_device.src_addr_widths = SDMA_DMA_BUSWIDTHS; in sdma_probe()
2115 sdma->dma_device.dst_addr_widths = SDMA_DMA_BUSWIDTHS; in sdma_probe()
2116 sdma->dma_device.directions = SDMA_DMA_DIRECTIONS; in sdma_probe()
2117 sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; in sdma_probe()
2118 sdma->dma_device.device_prep_dma_memcpy = sdma_prep_memcpy; in sdma_probe()
2119 sdma->dma_device.device_issue_pending = sdma_issue_pending; in sdma_probe()
2120 sdma->dma_device.copy_align = 2; in sdma_probe()
2121 dma_set_max_seg_size(sdma->dma_device.dev, SDMA_BD_MAX_CNT); in sdma_probe()
2125 ret = dma_async_device_register(&sdma->dma_device); in sdma_probe()
2127 dev_err(&pdev->dev, "unable to register\n"); in sdma_probe()
2134 dev_err(&pdev->dev, "failed to register controller\n"); in sdma_probe()
2138 spba_bus = of_find_compatible_node(NULL, NULL, "fsl,spba-bus"); in sdma_probe()
2141 sdma->spba_start_addr = spba_res.start; in sdma_probe()
2142 sdma->spba_end_addr = spba_res.end; in sdma_probe()
2154 ret = sdma_get_firmware(sdma, pdata->fw_name); in sdma_probe()
2156 dev_warn(&pdev->dev, "failed to get firmware from platform data\n"); in sdma_probe()
2163 ret = of_property_read_string(np, "fsl,sdma-ram-script-name", in sdma_probe()
2166 dev_warn(&pdev->dev, "failed to get firmware name\n"); in sdma_probe()
2170 dev_warn(&pdev->dev, "failed to get firmware from device tree\n"); in sdma_probe()
2177 dma_async_device_unregister(&sdma->dma_device); in sdma_probe()
2179 kfree(sdma->script_addrs); in sdma_probe()
2181 clk_unprepare(sdma->clk_ahb); in sdma_probe()
2183 clk_unprepare(sdma->clk_ipg); in sdma_probe()
2192 devm_free_irq(&pdev->dev, sdma->irq, sdma); in sdma_remove()
2193 dma_async_device_unregister(&sdma->dma_device); in sdma_remove()
2194 kfree(sdma->script_addrs); in sdma_remove()
2195 clk_unprepare(sdma->clk_ahb); in sdma_remove()
2196 clk_unprepare(sdma->clk_ipg); in sdma_remove()
2199 struct sdma_channel *sdmac = &sdma->channel[i]; in sdma_remove()
2201 tasklet_kill(&sdmac->vc.task); in sdma_remove()
2202 sdma_free_chan_resources(&sdmac->vc.chan); in sdma_remove()
2211 .name = "imx-sdma",
2224 MODULE_FIRMWARE("imx/sdma/sdma-imx6q.bin");
2227 MODULE_FIRMWARE("imx/sdma/sdma-imx7d.bin");