284 				unsigned int ae_csr, unsigned int csr_val)  in qat_hal_wr_indr_csr()  argument
294 		qat_hal_wr_ae_csr(handle, ae, ae_csr, csr_val);  in qat_hal_wr_indr_csr()
304 	unsigned int cur_ctx, csr_val;  in qat_hal_rd_indr_csr()  local
308 	csr_val = qat_hal_rd_ae_csr(handle, ae, ae_csr);  in qat_hal_rd_indr_csr()
311 	return csr_val;  in qat_hal_rd_indr_csr()
413 	unsigned int csr_val;  in qat_hal_init_esram()  local
419 	csr_val = ADF_CSR_RD(csr_addr, 0);  in qat_hal_init_esram()
420 	if ((csr_val & ESRAM_AUTO_TINIT) && (csr_val & ESRAM_AUTO_TINIT_DONE))  in qat_hal_init_esram()
423 	csr_val = ADF_CSR_RD(csr_addr, 0);  in qat_hal_init_esram()
424 	csr_val |= ESRAM_AUTO_TINIT;  in qat_hal_init_esram()
425 	ADF_CSR_WR(csr_addr, 0, csr_val);  in qat_hal_init_esram()
429 		csr_val = ADF_CSR_RD(csr_addr, 0);  in qat_hal_init_esram()
430 	} while (!(csr_val & ESRAM_AUTO_TINIT_DONE) && times--);  in qat_hal_init_esram()
591 	unsigned int csr_val = 0;  in qat_hal_clear_gpr()  local
596 		csr_val = qat_hal_rd_ae_csr(handle, ae, AE_MISC_CONTROL);  in qat_hal_clear_gpr()
597 		csr_val &= ~(1 << MMC_SHARE_CS_BITPOS);  in qat_hal_clear_gpr()
598 		qat_hal_wr_ae_csr(handle, ae, AE_MISC_CONTROL, csr_val);  in qat_hal_clear_gpr()
599 		csr_val = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES);  in qat_hal_clear_gpr()
600 		csr_val &= IGNORE_W1C_MASK;  in qat_hal_clear_gpr()
601 		csr_val |= CE_NN_MODE;  in qat_hal_clear_gpr()
602 		qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, csr_val);  in qat_hal_clear_gpr()
718 		unsigned int csr_val = 0;  in qat_hal_init()  local
720 		csr_val = qat_hal_rd_ae_csr(handle, ae, SIGNATURE_ENABLE);  in qat_hal_init()
721 		csr_val |= 0x1;  in qat_hal_init()
722 		qat_hal_wr_ae_csr(handle, ae, SIGNATURE_ENABLE, csr_val);  in qat_hal_init()
840 	unsigned int csr_val = 0, newcsr_val;  in qat_hal_exec_micro_inst()  local
899 	csr_val = qat_hal_rd_ae_csr(handle, ae, AE_MISC_CONTROL);  in qat_hal_exec_micro_inst()
900 	newcsr_val = CLR_BIT(csr_val, MMC_SHARE_CS_BITPOS);  in qat_hal_exec_micro_inst()