123 	writel(MTK_DFSE_THR_CTRL_EN | mask, cryp->base + DFE_THR_CTRL);  in mtk_desc_ring_link()
124 	writel(MTK_DFSE_THR_CTRL_EN | mask, cryp->base + DSE_THR_CTRL);  in mtk_desc_ring_link()
136 	writel(MTK_DFSE_MIN_DATA(ipbuf - 1) |  in mtk_dfe_dse_buf_setup()
142 	writel(MTK_DFSE_MIN_DATA(opbuf - 1) |  in mtk_dfe_dse_buf_setup()
146 	writel(MTK_IN_BUF_MIN_THRESH(ipbuf - 1) |  in mtk_dfe_dse_buf_setup()
150 	writel(MTK_IN_BUF_MIN_THRESH(itbuf - 1) |  in mtk_dfe_dse_buf_setup()
154 	writel(MTK_OUT_BUF_MIN_THRESH(opbuf - 1) |  in mtk_dfe_dse_buf_setup()
158 	writel(0, cryp->base + PE_OUT_TBUF_THRESH);  in mtk_dfe_dse_buf_setup()
159 	writel(0, cryp->base + PE_OUT_BUF_CTRL);  in mtk_dfe_dse_buf_setup()
177 		writel(0, cryp->base + DFE_THR_CTRL);  in mtk_dfe_dse_state_check()
178 		writel(0, cryp->base + DSE_THR_CTRL);  in mtk_dfe_dse_state_check()
189 	writel(MTK_DFSE_THR_CTRL_RESET, cryp->base + DFE_THR_CTRL);  in mtk_dfe_dse_reset()
190 	writel(0, cryp->base + DFE_PRIO_0);  in mtk_dfe_dse_reset()
191 	writel(0, cryp->base + DFE_PRIO_1);  in mtk_dfe_dse_reset()
192 	writel(0, cryp->base + DFE_PRIO_2);  in mtk_dfe_dse_reset()
193 	writel(0, cryp->base + DFE_PRIO_3);  in mtk_dfe_dse_reset()
195 	writel(MTK_DFSE_THR_CTRL_RESET, cryp->base + DSE_THR_CTRL);  in mtk_dfe_dse_reset()
196 	writel(0, cryp->base + DSE_PRIO_0);  in mtk_dfe_dse_reset()
197 	writel(0, cryp->base + DSE_PRIO_1);  in mtk_dfe_dse_reset()
198 	writel(0, cryp->base + DSE_PRIO_2);  in mtk_dfe_dse_reset()
199 	writel(0, cryp->base + DSE_PRIO_3);  in mtk_dfe_dse_reset()
212 	writel(0, cryp->base + CDR_CFG(i));  in mtk_cmd_desc_ring_setup()
215 	writel(MTK_CNT_RST, cryp->base + CDR_PREP_COUNT(i));  in mtk_cmd_desc_ring_setup()
216 	writel(MTK_CNT_RST, cryp->base + CDR_PROC_COUNT(i));  in mtk_cmd_desc_ring_setup()
218 	writel(0, cryp->base + CDR_PREP_PNTR(i));  in mtk_cmd_desc_ring_setup()
219 	writel(0, cryp->base + CDR_PROC_PNTR(i));  in mtk_cmd_desc_ring_setup()
220 	writel(0, cryp->base + CDR_DMA_CFG(i));  in mtk_cmd_desc_ring_setup()
223 	writel(0, cryp->base + CDR_BASE_ADDR_HI(i));  in mtk_cmd_desc_ring_setup()
224 	writel(cryp->ring[i]->cmd_dma, cryp->base + CDR_BASE_ADDR_LO(i));  in mtk_cmd_desc_ring_setup()
226 	writel(MTK_DESC_RING_SZ, cryp->base + CDR_RING_SIZE(i));  in mtk_cmd_desc_ring_setup()
229 	writel(MTK_CDR_STAT_CLR, cryp->base + CDR_STAT(i));  in mtk_cmd_desc_ring_setup()
235 	writel(MTK_DESC_SIZE(MTK_DESC_SZ) |  in mtk_cmd_desc_ring_setup()
240 	writel(MTK_DESC_FETCH_SIZE(count * MTK_DESC_OFF) |  in mtk_cmd_desc_ring_setup()
252 	writel(0, cryp->base + RDR_CFG(i));  in mtk_res_desc_ring_setup()
255 	writel(MTK_CNT_RST, cryp->base + RDR_PREP_COUNT(i));  in mtk_res_desc_ring_setup()
256 	writel(MTK_CNT_RST, cryp->base + RDR_PROC_COUNT(i));  in mtk_res_desc_ring_setup()
258 	writel(0, cryp->base + RDR_PREP_PNTR(i));  in mtk_res_desc_ring_setup()
259 	writel(0, cryp->base + RDR_PROC_PNTR(i));  in mtk_res_desc_ring_setup()
260 	writel(0, cryp->base + RDR_DMA_CFG(i));  in mtk_res_desc_ring_setup()
263 	writel(0, cryp->base + RDR_BASE_ADDR_HI(i));  in mtk_res_desc_ring_setup()
264 	writel(cryp->ring[i]->res_dma, cryp->base + RDR_BASE_ADDR_LO(i));  in mtk_res_desc_ring_setup()
266 	writel(MTK_DESC_RING_SZ, cryp->base + RDR_RING_SIZE(i));  in mtk_res_desc_ring_setup()
267 	writel(MTK_RDR_STAT_CLR, cryp->base + RDR_STAT(i));  in mtk_res_desc_ring_setup()
274 	writel(MTK_RDR_PROC_THRESH | MTK_RDR_PROC_MODE,  in mtk_res_desc_ring_setup()
282 	writel(MTK_DESC_SIZE(MTK_DESC_SZ) | MTK_DESC_OFFSET(MTK_DESC_OFF),  in mtk_res_desc_ring_setup()
289 	writel(MTK_DESC_FETCH_SIZE(count * MTK_DESC_OFF) |  in mtk_res_desc_ring_setup()
309 	writel(0, cryp->base + EIP97_MST_CTRL);  in mtk_packet_engine_setup()
315 	writel(val, cryp->base + HIA_MST_CTRL);  in mtk_packet_engine_setup()
333 	writel(MTK_PE_TK_LOC_AVL | MTK_PE_PROC_HELD | MTK_PE_TK_TIMEOUT_EN,  in mtk_packet_engine_setup()
337 	writel(MTK_AIC_G_CLR, cryp->base + AIC_G_ACK);  in mtk_packet_engine_setup()
338 	writel(MTK_PE_INPUT_DMA_ERR | MTK_PE_OUTPUT_DMA_ERR |  in mtk_packet_engine_setup()
384 		writel(0, cryp->base + AIC_G_ENABLE_CTRL);  in mtk_aic_init()
385 		writel(0, cryp->base + AIC_G_POL_CTRL);  in mtk_aic_init()
386 		writel(0, cryp->base + AIC_G_TYPE_CTRL);  in mtk_aic_init()
387 		writel(0, cryp->base + AIC_G_ENABLE_SET);  in mtk_aic_init()
389 		writel(0, cryp->base + AIC_ENABLE_CTRL(hw));  in mtk_aic_init()
390 		writel(0, cryp->base + AIC_POL_CTRL(hw));  in mtk_aic_init()
391 		writel(0, cryp->base + AIC_TYPE_CTRL(hw));  in mtk_aic_init()
392 		writel(0, cryp->base + AIC_ENABLE_SET(hw));  in mtk_aic_init()