254 	void __iomem *base = qm->io_base;  in hisi_zip_set_user_domain_and_cache()
308 		       qm->io_base + HZIP_CORE_INT_MASK_REG);  in hisi_zip_hw_error_enable()
314 	writel(HZIP_CORE_INT_MASK_ALL, qm->io_base + HZIP_CORE_INT_SOURCE);  in hisi_zip_hw_error_enable()
317 	writel(0x1, qm->io_base + HZIP_CORE_INT_RAS_CE_ENB);  in hisi_zip_hw_error_enable()
318 	writel(0x0, qm->io_base + HZIP_CORE_INT_RAS_FE_ENB);  in hisi_zip_hw_error_enable()
320 	       qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);  in hisi_zip_hw_error_enable()
323 	writel(0, qm->io_base + HZIP_CORE_INT_MASK_REG);  in hisi_zip_hw_error_enable()
326 	val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);  in hisi_zip_hw_error_enable()
328 	writel(val, qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);  in hisi_zip_hw_error_enable()
336 	writel(HZIP_CORE_INT_MASK_ALL, qm->io_base + HZIP_CORE_INT_MASK_REG);  in hisi_zip_hw_error_disable()
339 	val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);  in hisi_zip_hw_error_disable()
341 	writel(val, qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);  in hisi_zip_hw_error_disable()
355 	return readl(qm->io_base + QM_DFX_MB_CNT_VF);  in current_qm_read()
379 	writel(val, qm->io_base + QM_DFX_MB_CNT_VF);  in current_qm_write()
380 	writel(val, qm->io_base + QM_DFX_DB_CNT_VF);  in current_qm_write()
383 	      (readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) & CURRENT_Q_MASK);  in current_qm_write()
384 	writel(tmp, qm->io_base + QM_DFX_SQE_CNT_VF_SQN);  in current_qm_write()
387 	      (readl(qm->io_base + QM_DFX_CQE_CNT_VF_CQN) & CURRENT_Q_MASK);  in current_qm_write()
388 	writel(tmp, qm->io_base + QM_DFX_CQE_CNT_VF_CQN);  in current_qm_write()
397 	return readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) &  in clear_enable_read()
409 	tmp = (readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) &  in clear_enable_write()
411 	writel(tmp, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE);  in clear_enable_write()
537 		regset->base = qm->io_base + core_offsets[i];  in hisi_zip_core_debug_init()
618 	writel(0x0, qm->io_base + QM_DFX_MB_CNT_VF);  in hisi_zip_debug_regs_clear()
619 	writel(0x0, qm->io_base + QM_DFX_DB_CNT_VF);  in hisi_zip_debug_regs_clear()
622 	writel(HZIP_RD_CNT_CLR_CE_EN, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE);  in hisi_zip_debug_regs_clear()
625 			readl(qm->io_base + core_offsets[i] +  in hisi_zip_debug_regs_clear()
629 	writel(0x0, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE);  in hisi_zip_debug_regs_clear()
656 				err_val = readl(qm->io_base +  in hisi_zip_log_hw_error()
669 	return readl(qm->io_base + HZIP_CORE_INT_STATUS);  in hisi_zip_get_hw_err_status()
674 	writel(err_sts, qm->io_base + HZIP_CORE_INT_SOURCE);  in hisi_zip_clear_hw_err_status()
681 	val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);  in hisi_zip_open_axi_master_ooo()
684 	       qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);  in hisi_zip_open_axi_master_ooo()
687 	       qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);  in hisi_zip_open_axi_master_ooo()
695 	nfe_enb = readl(qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);  in hisi_zip_close_axi_master_ooo()
697 	       qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);  in hisi_zip_close_axi_master_ooo()
701 	       qm->io_base + HZIP_CORE_INT_SET);  in hisi_zip_close_axi_master_ooo()