87 #define SEC_ADDR(qm, offset) ((qm)->io_base + (offset) + \
257 	reg = readl_relaxed(qm->io_base + SEC_ENGINE_PF_CFG_OFF +  in sec_get_endian()
306 	       qm->io_base + AM_CFG_SINGLE_PORT_MAX_TRANS);  in sec_engine_init()
330 	writel(AXUSER_BASE, qm->io_base + QM_ARUSER_M_CFG_1);  in sec_set_user_domain_and_cache()
331 	writel(ARUSER_M_CFG_ENABLE, qm->io_base + QM_ARUSER_M_CFG_ENABLE);  in sec_set_user_domain_and_cache()
332 	writel(AXUSER_BASE, qm->io_base + QM_AWUSER_M_CFG_1);  in sec_set_user_domain_and_cache()
333 	writel(AWUSER_M_CFG_ENABLE, qm->io_base + QM_AWUSER_M_CFG_ENABLE);  in sec_set_user_domain_and_cache()
334 	writel(WUSER_M_CFG_ENABLE, qm->io_base + QM_WUSER_M_CFG_ENABLE);  in sec_set_user_domain_and_cache()
337 	writel(AXI_M_CFG, qm->io_base + QM_AXI_M_CFG);  in sec_set_user_domain_and_cache()
338 	writel(AXI_M_CFG_ENABLE, qm->io_base + QM_AXI_M_CFG_ENABLE);  in sec_set_user_domain_and_cache()
341 	writel(PEH_AXUSER_CFG, qm->io_base + QM_PEH_AXUSER_CFG);  in sec_set_user_domain_and_cache()
342 	writel(PEH_AXUSER_CFG_ENABLE, qm->io_base + QM_PEH_AXUSER_CFG_ENABLE);  in sec_set_user_domain_and_cache()
347 	       FIELD_PREP(CQC_CACHE_WB_THRD, 1), qm->io_base + QM_CACHE_CTL);  in sec_set_user_domain_and_cache()
358 	writel(0x0, qm->io_base + QM_DFX_MB_CNT_VF);  in sec_debug_regs_clear()
359 	writel(0x0, qm->io_base + QM_DFX_DB_CNT_VF);  in sec_debug_regs_clear()
362 	writel(0x1, qm->io_base + SEC_CTRL_CNT_CLR_CE);  in sec_debug_regs_clear()
364 		readl(qm->io_base + sec_dfx_regs[i].offset);  in sec_debug_regs_clear()
367 	writel(0x0, qm->io_base + SEC_CTRL_CNT_CLR_CE);  in sec_debug_regs_clear()
377 		writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK);  in sec_hw_error_enable()
385 	writel(SEC_CORE_INT_CLEAR, qm->io_base + SEC_CORE_INT_SOURCE);  in sec_hw_error_enable()
388 	writel(SEC_CORE_INT_ENABLE, qm->io_base + SEC_CORE_INT_MASK);  in sec_hw_error_enable()
391 	writel(SEC_RAS_CE_ENB_MSK, qm->io_base + SEC_RAS_CE_REG);  in sec_hw_error_enable()
392 	writel(SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_RAS_FE_REG);  in sec_hw_error_enable()
393 	writel(SEC_RAS_NFE_ENB_MSK, qm->io_base + SEC_RAS_NFE_REG);  in sec_hw_error_enable()
408 	writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_CE_REG);  in sec_hw_error_disable()
409 	writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_FE_REG);  in sec_hw_error_disable()
410 	writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_NFE_REG);  in sec_hw_error_disable()
413 	writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK);  in sec_hw_error_disable()
425 	return readl(qm->io_base + QM_DFX_MB_CNT_VF);  in sec_current_qm_read()
451 	writel(val, qm->io_base + QM_DFX_MB_CNT_VF);  in sec_current_qm_write()
452 	writel(val, qm->io_base + QM_DFX_DB_CNT_VF);  in sec_current_qm_write()
455 	      (readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) & CURRENT_Q_MASK);  in sec_current_qm_write()
456 	writel(tmp, qm->io_base + QM_DFX_SQE_CNT_VF_SQN);  in sec_current_qm_write()
459 	      (readl(qm->io_base + QM_DFX_CQE_CNT_VF_CQN) & CURRENT_Q_MASK);  in sec_current_qm_write()
460 	writel(tmp, qm->io_base + QM_DFX_CQE_CNT_VF_CQN);  in sec_current_qm_write()
469 	return readl(qm->io_base + SEC_CTRL_CNT_CLR_CE) &  in sec_clear_enable_read()
481 	tmp = (readl(qm->io_base + SEC_CTRL_CNT_CLR_CE) &  in sec_clear_enable_write()
483 	writel(tmp, qm->io_base + SEC_CTRL_CNT_CLR_CE);  in sec_clear_enable_write()
610 	regset->base = qm->io_base;  in sec_core_debug_init()
689 				err_val = readl(qm->io_base +  in sec_log_hw_error()
701 	return readl(qm->io_base + SEC_CORE_INT_STATUS);  in sec_get_hw_err_status()
706 	writel(err_sts, qm->io_base + SEC_CORE_INT_SOURCE);  in sec_clear_hw_err_status()