Lines Matching refs:SEC_CONTROL_REG
61 #define SEC_CONTROL_REG 0x0200 macro
258 SEC_ACC_COMMON_REG_OFF + SEC_CONTROL_REG); in sec_get_endian()
279 reg = readl_relaxed(SEC_ADDR(qm, SEC_CONTROL_REG)); in sec_engine_init()
281 writel_relaxed(reg, SEC_ADDR(qm, SEC_CONTROL_REG)); in sec_engine_init()
293 reg = readl_relaxed(SEC_ADDR(qm, SEC_CONTROL_REG)); in sec_engine_init()
295 writel_relaxed(reg, SEC_ADDR(qm, SEC_CONTROL_REG)); in sec_engine_init()
320 reg = readl_relaxed(SEC_ADDR(qm, SEC_CONTROL_REG)); in sec_engine_init()
322 writel_relaxed(reg, SEC_ADDR(qm, SEC_CONTROL_REG)); in sec_engine_init()
382 val = readl(SEC_ADDR(qm, SEC_CONTROL_REG)); in sec_hw_error_enable()
398 writel(val, SEC_ADDR(qm, SEC_CONTROL_REG)); in sec_hw_error_enable()
405 val = readl(SEC_ADDR(qm, SEC_CONTROL_REG)); in sec_hw_error_disable()
418 writel(val, SEC_ADDR(qm, SEC_CONTROL_REG)); in sec_hw_error_disable()
713 val = readl(SEC_ADDR(qm, SEC_CONTROL_REG)); in sec_open_axi_master_ooo()
714 writel(val & SEC_AXI_SHUTDOWN_DISABLE, SEC_ADDR(qm, SEC_CONTROL_REG)); in sec_open_axi_master_ooo()
715 writel(val | SEC_AXI_SHUTDOWN_ENABLE, SEC_ADDR(qm, SEC_CONTROL_REG)); in sec_open_axi_master_ooo()