87 #define SEC_ADDR(qm, offset) ((qm)->io_base + (offset) + \  macro
279 	reg = readl_relaxed(SEC_ADDR(qm, SEC_CONTROL_REG));  in sec_engine_init()
281 	writel_relaxed(reg, SEC_ADDR(qm, SEC_CONTROL_REG));  in sec_engine_init()
283 	writel_relaxed(0x1, SEC_ADDR(qm, SEC_MEM_START_INIT_REG));  in sec_engine_init()
285 	ret = readl_relaxed_poll_timeout(SEC_ADDR(qm, SEC_MEM_INIT_DONE_REG),  in sec_engine_init()
293 	reg = readl_relaxed(SEC_ADDR(qm, SEC_CONTROL_REG));  in sec_engine_init()
295 	writel_relaxed(reg, SEC_ADDR(qm, SEC_CONTROL_REG));  in sec_engine_init()
297 	reg = readl_relaxed(SEC_ADDR(qm, SEC_INTERFACE_USER_CTRL0_REG));  in sec_engine_init()
299 	writel_relaxed(reg, SEC_ADDR(qm, SEC_INTERFACE_USER_CTRL0_REG));  in sec_engine_init()
301 	reg = readl_relaxed(SEC_ADDR(qm, SEC_INTERFACE_USER_CTRL1_REG));  in sec_engine_init()
303 	writel_relaxed(reg, SEC_ADDR(qm, SEC_INTERFACE_USER_CTRL1_REG));  in sec_engine_init()
308 	writel(SEC_SAA_ENABLE, SEC_ADDR(qm, SEC_SAA_EN_REG));  in sec_engine_init()
312 		       SEC_ADDR(qm, SEC_BD_ERR_CHK_EN_REG0));  in sec_engine_init()
315 		       SEC_ADDR(qm, SEC_BD_ERR_CHK_EN_REG1));  in sec_engine_init()
317 		       SEC_ADDR(qm, SEC_BD_ERR_CHK_EN_REG3));  in sec_engine_init()
320 	reg = readl_relaxed(SEC_ADDR(qm, SEC_CONTROL_REG));  in sec_engine_init()
322 	writel_relaxed(reg, SEC_ADDR(qm, SEC_CONTROL_REG));  in sec_engine_init()
382 	val = readl(SEC_ADDR(qm, SEC_CONTROL_REG));  in sec_hw_error_enable()
398 	writel(val, SEC_ADDR(qm, SEC_CONTROL_REG));  in sec_hw_error_enable()
405 	val = readl(SEC_ADDR(qm, SEC_CONTROL_REG));  in sec_hw_error_disable()
418 	writel(val, SEC_ADDR(qm, SEC_CONTROL_REG));  in sec_hw_error_disable()
713 	val = readl(SEC_ADDR(qm, SEC_CONTROL_REG));  in sec_open_axi_master_ooo()
714 	writel(val & SEC_AXI_SHUTDOWN_DISABLE, SEC_ADDR(qm, SEC_CONTROL_REG));  in sec_open_axi_master_ooo()
715 	writel(val | SEC_AXI_SHUTDOWN_ENABLE, SEC_ADDR(qm, SEC_CONTROL_REG));  in sec_open_axi_master_ooo()