71 #define HPRE_ADDR(qm, offset)		((qm)->io_base + (offset))  macro
250 	val = readl(HPRE_ADDR(qm, QM_PEH_AXUSER_CFG));  in disable_flr_of_bme()
253 	writel(val, HPRE_ADDR(qm, QM_PEH_AXUSER_CFG));  in disable_flr_of_bme()
254 	writel(PEH_AXUSER_CFG_ENABLE, HPRE_ADDR(qm, QM_PEH_AXUSER_CFG_ENABLE));  in disable_flr_of_bme()
264 	writel(HPRE_QM_USR_CFG_MASK, HPRE_ADDR(qm, QM_ARUSER_M_CFG_ENABLE));  in hpre_set_user_domain_and_cache()
265 	writel(HPRE_QM_USR_CFG_MASK, HPRE_ADDR(qm, QM_AWUSER_M_CFG_ENABLE));  in hpre_set_user_domain_and_cache()
266 	writel_relaxed(HPRE_QM_AXI_CFG_MASK, HPRE_ADDR(qm, QM_AXI_M_CFG));  in hpre_set_user_domain_and_cache()
269 	val = readl_relaxed(HPRE_ADDR(qm, HPRE_QM_ABNML_INT_MASK));  in hpre_set_user_domain_and_cache()
271 	writel_relaxed(val, HPRE_ADDR(qm, HPRE_QM_ABNML_INT_MASK));  in hpre_set_user_domain_and_cache()
273 	writel(0x1, HPRE_ADDR(qm, HPRE_TYPES_ENB));  in hpre_set_user_domain_and_cache()
274 	writel(HPRE_QM_VFG_AX_MASK, HPRE_ADDR(qm, HPRE_VFG_AXCACHE));  in hpre_set_user_domain_and_cache()
275 	writel(0x0, HPRE_ADDR(qm, HPRE_BD_ENDIAN));  in hpre_set_user_domain_and_cache()
276 	writel(0x0, HPRE_ADDR(qm, HPRE_INT_MASK));  in hpre_set_user_domain_and_cache()
277 	writel(0x0, HPRE_ADDR(qm, HPRE_RAS_ECC_1BIT_TH));  in hpre_set_user_domain_and_cache()
278 	writel(0x0, HPRE_ADDR(qm, HPRE_POISON_BYPASS));  in hpre_set_user_domain_and_cache()
279 	writel(0x0, HPRE_ADDR(qm, HPRE_COMM_CNT_CLR_CE));  in hpre_set_user_domain_and_cache()
280 	writel(0x0, HPRE_ADDR(qm, HPRE_ECC_BYPASS));  in hpre_set_user_domain_and_cache()
282 	writel(HPRE_BD_USR_MASK, HPRE_ADDR(qm, HPRE_BD_ARUSR_CFG));  in hpre_set_user_domain_and_cache()
283 	writel(HPRE_BD_USR_MASK, HPRE_ADDR(qm, HPRE_BD_AWUSR_CFG));  in hpre_set_user_domain_and_cache()
284 	writel(0x1, HPRE_ADDR(qm, HPRE_RDCHN_INI_CFG));  in hpre_set_user_domain_and_cache()
285 	ret = readl_relaxed_poll_timeout(HPRE_ADDR(qm, HPRE_RDCHN_INI_ST), val,  in hpre_set_user_domain_and_cache()
299 		       HPRE_ADDR(qm, offset + HPRE_CORE_ENB));  in hpre_set_user_domain_and_cache()
300 		writel(0x1, HPRE_ADDR(qm, offset + HPRE_CORE_INI_CFG));  in hpre_set_user_domain_and_cache()
301 		ret = readl_relaxed_poll_timeout(HPRE_ADDR(qm, offset +  in hpre_set_user_domain_and_cache()
785 	       HPRE_ADDR(qm, HPRE_AM_OOO_SHUTDOWN_ENB));  in hpre_open_axi_master_ooo()
787 	       HPRE_ADDR(qm, HPRE_AM_OOO_SHUTDOWN_ENB));  in hpre_open_axi_master_ooo()