510 				 unsigned int *seq_size)  in cc_setup_readiv_desc()  argument
530 		hw_desc_init(&desc[*seq_size]);  in cc_setup_readiv_desc()
531 		set_dout_dlli(&desc[*seq_size], iv_dma_addr, ivsize, NS_BIT, 1);  in cc_setup_readiv_desc()
532 		set_cipher_config0(&desc[*seq_size], direction);  in cc_setup_readiv_desc()
533 		set_flow_mode(&desc[*seq_size], flow_mode);  in cc_setup_readiv_desc()
534 		set_cipher_mode(&desc[*seq_size], cipher_mode);  in cc_setup_readiv_desc()
537 			set_setup_mode(&desc[*seq_size], SETUP_WRITE_STATE1);  in cc_setup_readiv_desc()
539 			set_setup_mode(&desc[*seq_size], SETUP_WRITE_STATE0);  in cc_setup_readiv_desc()
541 		set_queue_last_ind(ctx_p->drvdata, &desc[*seq_size]);  in cc_setup_readiv_desc()
542 		(*seq_size)++;  in cc_setup_readiv_desc()
547 		hw_desc_init(&desc[*seq_size]);  in cc_setup_readiv_desc()
548 		set_setup_mode(&desc[*seq_size], SETUP_WRITE_STATE1);  in cc_setup_readiv_desc()
549 		set_cipher_mode(&desc[*seq_size], cipher_mode);  in cc_setup_readiv_desc()
550 		set_cipher_config0(&desc[*seq_size], direction);  in cc_setup_readiv_desc()
551 		set_flow_mode(&desc[*seq_size], flow_mode);  in cc_setup_readiv_desc()
552 		set_dout_dlli(&desc[*seq_size], iv_dma_addr, CC_AES_BLOCK_SIZE,  in cc_setup_readiv_desc()
554 		set_queue_last_ind(ctx_p->drvdata, &desc[*seq_size]);  in cc_setup_readiv_desc()
555 		(*seq_size)++;  in cc_setup_readiv_desc()
567 				 unsigned int *seq_size)  in cc_setup_state_desc()  argument
584 		hw_desc_init(&desc[*seq_size]);  in cc_setup_state_desc()
585 		set_din_type(&desc[*seq_size], DMA_DLLI, iv_dma_addr, ivsize,  in cc_setup_state_desc()
587 		set_cipher_config0(&desc[*seq_size], direction);  in cc_setup_state_desc()
588 		set_flow_mode(&desc[*seq_size], flow_mode);  in cc_setup_state_desc()
589 		set_cipher_mode(&desc[*seq_size], cipher_mode);  in cc_setup_state_desc()
592 			set_setup_mode(&desc[*seq_size], SETUP_LOAD_STATE1);  in cc_setup_state_desc()
594 			set_setup_mode(&desc[*seq_size], SETUP_LOAD_STATE0);  in cc_setup_state_desc()
596 		(*seq_size)++;  in cc_setup_state_desc()
611 				 unsigned int *seq_size)  in cc_setup_xex_state_desc()  argument
638 		hw_desc_init(&desc[*seq_size]);  in cc_setup_xex_state_desc()
639 		set_cipher_mode(&desc[*seq_size], cipher_mode);  in cc_setup_xex_state_desc()
640 		set_cipher_config0(&desc[*seq_size], direction);  in cc_setup_xex_state_desc()
642 			set_hw_crypto_key(&desc[*seq_size],  in cc_setup_xex_state_desc()
645 			set_din_type(&desc[*seq_size], DMA_DLLI,  in cc_setup_xex_state_desc()
649 		set_xex_data_unit_size(&desc[*seq_size], nbytes);  in cc_setup_xex_state_desc()
650 		set_flow_mode(&desc[*seq_size], S_DIN_to_AES2);  in cc_setup_xex_state_desc()
651 		set_key_size_aes(&desc[*seq_size], key_len);  in cc_setup_xex_state_desc()
652 		set_setup_mode(&desc[*seq_size], SETUP_LOAD_XEX_KEY);  in cc_setup_xex_state_desc()
653 		(*seq_size)++;  in cc_setup_xex_state_desc()
656 		hw_desc_init(&desc[*seq_size]);  in cc_setup_xex_state_desc()
657 		set_setup_mode(&desc[*seq_size], SETUP_LOAD_STATE1);  in cc_setup_xex_state_desc()
658 		set_cipher_mode(&desc[*seq_size], cipher_mode);  in cc_setup_xex_state_desc()
659 		set_cipher_config0(&desc[*seq_size], direction);  in cc_setup_xex_state_desc()
660 		set_key_size_aes(&desc[*seq_size], key_len);  in cc_setup_xex_state_desc()
661 		set_flow_mode(&desc[*seq_size], flow_mode);  in cc_setup_xex_state_desc()
662 		set_din_type(&desc[*seq_size], DMA_DLLI, iv_dma_addr,  in cc_setup_xex_state_desc()
664 		(*seq_size)++;  in cc_setup_xex_state_desc()
688 			      unsigned int *seq_size)  in cc_setup_key_desc()  argument
706 		hw_desc_init(&desc[*seq_size]);  in cc_setup_key_desc()
707 		set_cipher_mode(&desc[*seq_size], cipher_mode);  in cc_setup_key_desc()
708 		set_cipher_config0(&desc[*seq_size], direction);  in cc_setup_key_desc()
712 			set_key_size_aes(&desc[*seq_size], key_len);  in cc_setup_key_desc()
713 			set_cpp_crypto_key(&desc[*seq_size], ctx_p->cpp.slot);  in cc_setup_key_desc()
718 					set_hw_crypto_key(&desc[*seq_size],  in cc_setup_key_desc()
728 					set_din_type(&desc[*seq_size], DMA_DLLI,  in cc_setup_key_desc()
732 				set_key_size_aes(&desc[*seq_size], key_len);  in cc_setup_key_desc()
735 				set_din_type(&desc[*seq_size], DMA_DLLI,  in cc_setup_key_desc()
737 				set_key_size_des(&desc[*seq_size], key_len);  in cc_setup_key_desc()
739 			set_setup_mode(&desc[*seq_size], SETUP_LOAD_KEY0);  in cc_setup_key_desc()
741 		set_flow_mode(&desc[*seq_size], flow_mode);  in cc_setup_key_desc()
742 		(*seq_size)++;  in cc_setup_key_desc()
747 		hw_desc_init(&desc[*seq_size]);  in cc_setup_key_desc()
748 		set_cipher_mode(&desc[*seq_size], cipher_mode);  in cc_setup_key_desc()
749 		set_cipher_config0(&desc[*seq_size], direction);  in cc_setup_key_desc()
751 			set_hw_crypto_key(&desc[*seq_size],  in cc_setup_key_desc()
754 			set_din_type(&desc[*seq_size], DMA_DLLI, key_dma_addr,  in cc_setup_key_desc()
757 		set_key_size_aes(&desc[*seq_size], (key_len / 2));  in cc_setup_key_desc()
758 		set_flow_mode(&desc[*seq_size], flow_mode);  in cc_setup_key_desc()
759 		set_setup_mode(&desc[*seq_size], SETUP_LOAD_KEY0);  in cc_setup_key_desc()
760 		(*seq_size)++;  in cc_setup_key_desc()
771 			       struct cc_hw_desc desc[], unsigned int *seq_size)  in cc_setup_mlli_desc()  argument
782 		hw_desc_init(&desc[*seq_size]);  in cc_setup_mlli_desc()
783 		set_din_type(&desc[*seq_size], DMA_DLLI,  in cc_setup_mlli_desc()
786 		set_dout_sram(&desc[*seq_size],  in cc_setup_mlli_desc()
789 		set_flow_mode(&desc[*seq_size], BYPASS);  in cc_setup_mlli_desc()
790 		(*seq_size)++;  in cc_setup_mlli_desc()
798 			       unsigned int *seq_size)  in cc_setup_flow_desc()  argument
812 		hw_desc_init(&desc[*seq_size]);  in cc_setup_flow_desc()
813 		set_din_type(&desc[*seq_size], DMA_DLLI, sg_dma_address(src),  in cc_setup_flow_desc()
815 		set_dout_dlli(&desc[*seq_size], sg_dma_address(dst),  in cc_setup_flow_desc()
818 			set_queue_last_ind(ctx_p->drvdata, &desc[*seq_size]);  in cc_setup_flow_desc()
820 		set_flow_mode(&desc[*seq_size], flow_mode);  in cc_setup_flow_desc()
821 		(*seq_size)++;  in cc_setup_flow_desc()
823 		hw_desc_init(&desc[*seq_size]);  in cc_setup_flow_desc()
824 		set_din_type(&desc[*seq_size], DMA_MLLI,  in cc_setup_flow_desc()
831 			set_dout_mlli(&desc[*seq_size],  in cc_setup_flow_desc()
840 			set_dout_mlli(&desc[*seq_size],  in cc_setup_flow_desc()
848 			set_queue_last_ind(ctx_p->drvdata, &desc[*seq_size]);  in cc_setup_flow_desc()
850 		set_flow_mode(&desc[*seq_size], flow_mode);  in cc_setup_flow_desc()
851 		(*seq_size)++;  in cc_setup_flow_desc()