Lines Matching +full:offset +full:- +full:x
1 // SPDX-License-Identifier: GPL-2.0
14 * - NPS packet ring, AQMQ ring and ZQMQ ring
23 * nps_pkt_slc_isr - IRQ handler for NPS solicit port
31 struct nitrox_cmdq *cmdq = qvec->cmdq; in nps_pkt_slc_isr()
33 slc_cnts.value = readq(cmdq->compl_cnt_csr_addr); in nps_pkt_slc_isr()
36 tasklet_hi_schedule(&qvec->resp_tasklet); in nps_pkt_slc_isr()
49 dev_err_ratelimited(DEV(ndev), "NSP_CORE_INT 0x%016llx\n", value); in clear_nps_core_err_intr()
55 unsigned long value, offset; in clear_nps_pkt_err_intr() local
59 dev_err_ratelimited(DEV(ndev), "NPS_PKT_INT 0x%016llx\n", in clear_nps_pkt_err_intr()
63 offset = NPS_PKT_SLC_ERR_TYPE; in clear_nps_pkt_err_intr()
64 value = nitrox_read_csr(ndev, offset); in clear_nps_pkt_err_intr()
65 nitrox_write_csr(ndev, offset, value); in clear_nps_pkt_err_intr()
67 "NPS_PKT_SLC_ERR_TYPE 0x%016lx\n", value); in clear_nps_pkt_err_intr()
69 offset = NPS_PKT_SLC_RERR_LO; in clear_nps_pkt_err_intr()
70 value = nitrox_read_csr(ndev, offset); in clear_nps_pkt_err_intr()
71 nitrox_write_csr(ndev, offset, value); in clear_nps_pkt_err_intr()
77 "NPS_PKT_SLC_RERR_LO 0x%016lx\n", value); in clear_nps_pkt_err_intr()
79 offset = NPS_PKT_SLC_RERR_HI; in clear_nps_pkt_err_intr()
80 value = nitrox_read_csr(ndev, offset); in clear_nps_pkt_err_intr()
81 nitrox_write_csr(ndev, offset, value); in clear_nps_pkt_err_intr()
83 "NPS_PKT_SLC_RERR_HI 0x%016lx\n", value); in clear_nps_pkt_err_intr()
87 offset = NPS_PKT_IN_ERR_TYPE; in clear_nps_pkt_err_intr()
88 value = nitrox_read_csr(ndev, offset); in clear_nps_pkt_err_intr()
89 nitrox_write_csr(ndev, offset, value); in clear_nps_pkt_err_intr()
91 "NPS_PKT_IN_ERR_TYPE 0x%016lx\n", value); in clear_nps_pkt_err_intr()
92 offset = NPS_PKT_IN_RERR_LO; in clear_nps_pkt_err_intr()
93 value = nitrox_read_csr(ndev, offset); in clear_nps_pkt_err_intr()
94 nitrox_write_csr(ndev, offset, value); in clear_nps_pkt_err_intr()
100 "NPS_PKT_IN_RERR_LO 0x%016lx\n", value); in clear_nps_pkt_err_intr()
102 offset = NPS_PKT_IN_RERR_HI; in clear_nps_pkt_err_intr()
103 value = nitrox_read_csr(ndev, offset); in clear_nps_pkt_err_intr()
104 nitrox_write_csr(ndev, offset, value); in clear_nps_pkt_err_intr()
106 "NPS_PKT_IN_RERR_HI 0x%016lx\n", value); in clear_nps_pkt_err_intr()
116 dev_err_ratelimited(DEV(ndev), "POM_INT 0x%016llx\n", value); in clear_pom_err_intr()
125 dev_err_ratelimited(DEV(ndev), "PEM(0)_INT 0x%016llx\n", value); in clear_pem_err_intr()
131 u64 value, offset; in clear_lbc_err_intr() local
135 dev_err_ratelimited(DEV(ndev), "LBC_INT 0x%016llx\n", lbc_int.value); in clear_lbc_err_intr()
139 offset = EFL_CORE_VF_ERR_INT0X(i); in clear_lbc_err_intr()
140 value = nitrox_read_csr(ndev, offset); in clear_lbc_err_intr()
141 nitrox_write_csr(ndev, offset, value); in clear_lbc_err_intr()
142 offset = EFL_CORE_VF_ERR_INT1X(i); in clear_lbc_err_intr()
143 value = nitrox_read_csr(ndev, offset); in clear_lbc_err_intr()
144 nitrox_write_csr(ndev, offset, value); in clear_lbc_err_intr()
154 offset = LBC_PLM_VF1_64_INT; in clear_lbc_err_intr()
155 value = nitrox_read_csr(ndev, offset); in clear_lbc_err_intr()
156 nitrox_write_csr(ndev, offset, value); in clear_lbc_err_intr()
157 offset = LBC_PLM_VF65_128_INT; in clear_lbc_err_intr()
158 value = nitrox_read_csr(ndev, offset); in clear_lbc_err_intr()
159 nitrox_write_csr(ndev, offset, value); in clear_lbc_err_intr()
163 offset = LBC_ELM_VF1_64_INT; in clear_lbc_err_intr()
164 value = nitrox_read_csr(ndev, offset); in clear_lbc_err_intr()
165 nitrox_write_csr(ndev, offset, value); in clear_lbc_err_intr()
166 offset = LBC_ELM_VF65_128_INT; in clear_lbc_err_intr()
167 value = nitrox_read_csr(ndev, offset); in clear_lbc_err_intr()
168 nitrox_write_csr(ndev, offset, value); in clear_lbc_err_intr()
179 u64 value, offset; in clear_efl_err_intr() local
181 offset = EFL_CORE_INTX(i); in clear_efl_err_intr()
182 core_int.value = nitrox_read_csr(ndev, offset); in clear_efl_err_intr()
183 nitrox_write_csr(ndev, offset, core_int.value); in clear_efl_err_intr()
184 dev_err_ratelimited(DEV(ndev), "ELF_CORE(%d)_INT 0x%016llx\n", in clear_efl_err_intr()
187 offset = EFL_CORE_SE_ERR_INTX(i); in clear_efl_err_intr()
188 value = nitrox_read_csr(ndev, offset); in clear_efl_err_intr()
189 nitrox_write_csr(ndev, offset, value); in clear_efl_err_intr()
200 dev_err_ratelimited(DEV(ndev), "BMI_INT 0x%016llx\n", value); in clear_bmi_err_intr()
206 struct nitrox_device *ndev = qvec->ndev; in nps_core_int_tasklet()
209 if (ndev->mode == __NDEV_MODE_PF) { in nps_core_int_tasklet()
219 * nps_core_int_isr - interrupt handler for NITROX errors and
225 struct nitrox_device *ndev = qvec->ndev; in nps_core_int_isr()
264 struct pci_dev *pdev = ndev->pdev; in nitrox_unregister_interrupts()
267 for (i = 0; i < ndev->num_vecs; i++) { in nitrox_unregister_interrupts()
271 qvec = ndev->qvec + i; in nitrox_unregister_interrupts()
272 if (!qvec->valid) in nitrox_unregister_interrupts()
280 tasklet_disable(&qvec->resp_tasklet); in nitrox_unregister_interrupts()
281 tasklet_kill(&qvec->resp_tasklet); in nitrox_unregister_interrupts()
282 qvec->valid = false; in nitrox_unregister_interrupts()
284 kfree(ndev->qvec); in nitrox_unregister_interrupts()
285 ndev->qvec = NULL; in nitrox_unregister_interrupts()
291 struct pci_dev *pdev = ndev->pdev; in nitrox_register_interrupts()
297 * PF MSI-X vectors in nitrox_register_interrupts()
310 /* Enable MSI-X */ in nitrox_register_interrupts()
316 ndev->num_vecs = nr_vecs; in nitrox_register_interrupts()
318 ndev->qvec = kcalloc(nr_vecs, sizeof(*qvec), GFP_KERNEL); in nitrox_register_interrupts()
319 if (!ndev->qvec) { in nitrox_register_interrupts()
321 return -ENOMEM; in nitrox_register_interrupts()
325 for (i = PKT_RING_MSIX_BASE; i < (nr_vecs - 1); i += NR_RING_VECTORS) { in nitrox_register_interrupts()
326 qvec = &ndev->qvec[i]; in nitrox_register_interrupts()
328 qvec->ring = i / NR_RING_VECTORS; in nitrox_register_interrupts()
329 if (qvec->ring >= ndev->nr_queues) in nitrox_register_interrupts()
332 qvec->cmdq = &ndev->pkt_inq[qvec->ring]; in nitrox_register_interrupts()
333 snprintf(qvec->name, IRQ_NAMESZ, "nitrox-pkt%d", qvec->ring); in nitrox_register_interrupts()
336 ret = request_irq(vec, nps_pkt_slc_isr, 0, qvec->name, qvec); in nitrox_register_interrupts()
339 qvec->ring); in nitrox_register_interrupts()
342 cpu = qvec->ring % num_online_cpus(); in nitrox_register_interrupts()
345 tasklet_init(&qvec->resp_tasklet, pkt_slc_resp_tasklet, in nitrox_register_interrupts()
347 qvec->valid = true; in nitrox_register_interrupts()
352 qvec = &ndev->qvec[i]; in nitrox_register_interrupts()
353 qvec->ndev = ndev; in nitrox_register_interrupts()
355 snprintf(qvec->name, IRQ_NAMESZ, "nitrox-core-int%d", i); in nitrox_register_interrupts()
358 ret = request_irq(vec, nps_core_int_isr, 0, qvec->name, qvec); in nitrox_register_interrupts()
360 dev_err(DEV(ndev), "irq failed for nitrox-core-int%d\n", i); in nitrox_register_interrupts()
366 tasklet_init(&qvec->resp_tasklet, nps_core_int_tasklet, in nitrox_register_interrupts()
368 qvec->valid = true; in nitrox_register_interrupts()
379 struct pci_dev *pdev = ndev->pdev; in nitrox_sriov_unregister_interrupts()
382 for (i = 0; i < ndev->num_vecs; i++) { in nitrox_sriov_unregister_interrupts()
386 qvec = ndev->qvec + i; in nitrox_sriov_unregister_interrupts()
387 if (!qvec->valid) in nitrox_sriov_unregister_interrupts()
390 vec = ndev->iov.msix.vector; in nitrox_sriov_unregister_interrupts()
394 tasklet_disable(&qvec->resp_tasklet); in nitrox_sriov_unregister_interrupts()
395 tasklet_kill(&qvec->resp_tasklet); in nitrox_sriov_unregister_interrupts()
396 qvec->valid = false; in nitrox_sriov_unregister_interrupts()
398 kfree(ndev->qvec); in nitrox_sriov_unregister_interrupts()
399 ndev->qvec = NULL; in nitrox_sriov_unregister_interrupts()
405 struct pci_dev *pdev = ndev->pdev; in nitrox_sriov_register_interupts()
412 * for PF in SR-IOV mode. in nitrox_sriov_register_interupts()
414 ndev->iov.msix.entry = NON_RING_MSIX_BASE; in nitrox_sriov_register_interupts()
415 ret = pci_enable_msix_exact(pdev, &ndev->iov.msix, NR_NON_RING_VECTORS); in nitrox_sriov_register_interupts()
417 dev_err(DEV(ndev), "failed to allocate nps-core-int%d\n", in nitrox_sriov_register_interupts()
425 return -ENOMEM; in nitrox_sriov_register_interupts()
427 qvec->ndev = ndev; in nitrox_sriov_register_interupts()
429 ndev->qvec = qvec; in nitrox_sriov_register_interupts()
430 ndev->num_vecs = NR_NON_RING_VECTORS; in nitrox_sriov_register_interupts()
431 snprintf(qvec->name, IRQ_NAMESZ, "nitrox-core-int%d", in nitrox_sriov_register_interupts()
434 vec = ndev->iov.msix.vector; in nitrox_sriov_register_interupts()
435 ret = request_irq(vec, nps_core_int_isr, 0, qvec->name, qvec); in nitrox_sriov_register_interupts()
437 dev_err(DEV(ndev), "irq failed for nitrox-core-int%d\n", in nitrox_sriov_register_interupts()
444 tasklet_init(&qvec->resp_tasklet, nps_core_int_tasklet, in nitrox_sriov_register_interupts()
446 qvec->valid = true; in nitrox_sriov_register_interupts()