Lines Matching +full:0 +full:x40000
21 #define EMU_BIST_STATUSX(_i) (0x1402700 + ((_i) * 0x40000))
22 #define UCD_BIST_STATUS 0x12C0070
23 #define NPS_CORE_BIST_REG 0x10000E8
24 #define NPS_CORE_NPC_BIST_REG 0x1000128
25 #define NPS_PKT_SLC_BIST_REG 0x1040088
26 #define NPS_PKT_IN_BIST_REG 0x1040100
27 #define POM_BIST_REG 0x11C0100
28 #define BMI_BIST_REG 0x1140080
29 #define EFL_CORE_BIST_REGX(_i) (0x1240100 + ((_i) * 0x400))
30 #define EFL_TOP_BIST_STAT 0x1241090
31 #define BMO_BIST_REG 0x1180080
32 #define LBC_BIST_STATUS 0x1200020
33 #define PEM_BIST_STATUSX(_i) (0x1080468 | ((_i) << 18))
36 #define EMU_SE_ENABLEX(_i) (0x1400000 + ((_i) * 0x40000))
37 #define EMU_AE_ENABLEX(_i) (0x1400008 + ((_i) * 0x40000))
38 #define EMU_WD_INT_ENA_W1SX(_i) (0x1402318 + ((_i) * 0x40000))
39 #define EMU_GE_INT_ENA_W1SX(_i) (0x1402518 + ((_i) * 0x40000))
40 #define EMU_FUSE_MAPX(_i) (0x1402708 + ((_i) * 0x40000))
43 #define UCD_SE_EID_UCODE_BLOCK_NUMX(_i) (0x12C0000 + ((_i) * 0x1000))
44 #define UCD_AE_EID_UCODE_BLOCK_NUMX(_i) (0x12C0008 + ((_i) * 0x800))
45 #define UCD_UCODE_LOAD_BLOCK_NUM 0x12C0010
46 #define UCD_UCODE_LOAD_IDX_DATAX(_i) (0x12C0018 + ((_i) * 0x20))
47 #define UCD_SE_CNTX(_i) (0x12C0040 + ((_i) * 0x1000))
48 #define UCD_AE_CNTX(_i) (0x12C0048 + ((_i) * 0x800))
51 #define AQM_CTL 0x1300000
52 #define AQM_INT 0x1300008
53 #define AQM_DBELL_OVF_LO 0x1300010
54 #define AQM_DBELL_OVF_HI 0x1300018
55 #define AQM_DBELL_OVF_LO_W1S 0x1300020
56 #define AQM_DBELL_OVF_LO_ENA_W1C 0x1300028
57 #define AQM_DBELL_OVF_LO_ENA_W1S 0x1300030
58 #define AQM_DBELL_OVF_HI_W1S 0x1300038
59 #define AQM_DBELL_OVF_HI_ENA_W1C 0x1300040
60 #define AQM_DBELL_OVF_HI_ENA_W1S 0x1300048
61 #define AQM_DMA_RD_ERR_LO 0x1300050
62 #define AQM_DMA_RD_ERR_HI 0x1300058
63 #define AQM_DMA_RD_ERR_LO_W1S 0x1300060
64 #define AQM_DMA_RD_ERR_LO_ENA_W1C 0x1300068
65 #define AQM_DMA_RD_ERR_LO_ENA_W1S 0x1300070
66 #define AQM_DMA_RD_ERR_HI_W1S 0x1300078
67 #define AQM_DMA_RD_ERR_HI_ENA_W1C 0x1300080
68 #define AQM_DMA_RD_ERR_HI_ENA_W1S 0x1300088
69 #define AQM_EXEC_NA_LO 0x1300090
70 #define AQM_EXEC_NA_HI 0x1300098
71 #define AQM_EXEC_NA_LO_W1S 0x13000A0
72 #define AQM_EXEC_NA_LO_ENA_W1C 0x13000A8
73 #define AQM_EXEC_NA_LO_ENA_W1S 0x13000B0
74 #define AQM_EXEC_NA_HI_W1S 0x13000B8
75 #define AQM_EXEC_NA_HI_ENA_W1C 0x13000C0
76 #define AQM_EXEC_NA_HI_ENA_W1S 0x13000C8
77 #define AQM_EXEC_ERR_LO 0x13000D0
78 #define AQM_EXEC_ERR_HI 0x13000D8
79 #define AQM_EXEC_ERR_LO_W1S 0x13000E0
80 #define AQM_EXEC_ERR_LO_ENA_W1C 0x13000E8
81 #define AQM_EXEC_ERR_LO_ENA_W1S 0x13000F0
82 #define AQM_EXEC_ERR_HI_W1S 0x13000F8
83 #define AQM_EXEC_ERR_HI_ENA_W1C 0x1300100
84 #define AQM_EXEC_ERR_HI_ENA_W1S 0x1300108
85 #define AQM_ECC_INT 0x1300110
86 #define AQM_ECC_INT_W1S 0x1300118
87 #define AQM_ECC_INT_ENA_W1C 0x1300120
88 #define AQM_ECC_INT_ENA_W1S 0x1300128
89 #define AQM_ECC_CTL 0x1300130
90 #define AQM_BIST_STATUS 0x1300138
91 #define AQM_CMD_INF_THRX(x) (0x1300400 + ((x) * 0x8))
92 #define AQM_CMD_INFX(x) (0x1300800 + ((x) * 0x8))
93 #define AQM_GRP_EXECMSK_LOX(x) (0x1300C00 + ((x) * 0x10))
94 #define AQM_GRP_EXECMSK_HIX(x) (0x1300C08 + ((x) * 0x10))
95 #define AQM_ACTIVITY_STAT_LO 0x1300C80
96 #define AQM_ACTIVITY_STAT_HI 0x1300C88
97 #define AQM_Q_CMD_PROCX(x) (0x1301000 + ((x) * 0x8))
98 #define AQM_PERF_CTL_LO 0x1301400
99 #define AQM_PERF_CTL_HI 0x1301408
100 #define AQM_PERF_CNT 0x1301410
102 #define AQMQ_DRBLX(x) (0x20000 + ((x) * 0x40000))
103 #define AQMQ_QSZX(x) (0x20008 + ((x) * 0x40000))
104 #define AQMQ_BADRX(x) (0x20010 + ((x) * 0x40000))
105 #define AQMQ_NXT_CMDX(x) (0x20018 + ((x) * 0x40000))
106 #define AQMQ_CMD_CNTX(x) (0x20020 + ((x) * 0x40000))
107 #define AQMQ_CMP_THRX(x) (0x20028 + ((x) * 0x40000))
108 #define AQMQ_CMP_CNTX(x) (0x20030 + ((x) * 0x40000))
109 #define AQMQ_TIM_LDX(x) (0x20038 + ((x) * 0x40000))
110 #define AQMQ_TIMERX(x) (0x20040 + ((x) * 0x40000))
111 #define AQMQ_ENX(x) (0x20048 + ((x) * 0x40000))
112 #define AQMQ_ACTIVITY_STATX(x) (0x20050 + ((x) * 0x40000))
113 #define AQM_VF_CMP_STATX(x) (0x28000 + ((x) * 0x40000))
116 #define NPS_CORE_GBL_VFCFG 0x1000000
117 #define NPS_CORE_CONTROL 0x1000008
118 #define NPS_CORE_INT_ACTIVE 0x1000080
119 #define NPS_CORE_INT 0x10000A0
120 #define NPS_CORE_INT_ENA_W1S 0x10000B8
121 #define NPS_STATS_PKT_DMA_RD_CNT 0x1000180
122 #define NPS_STATS_PKT_DMA_WR_CNT 0x1000190
125 #define NPS_PKT_INT 0x1040018
126 #define NPS_PKT_MBOX_INT_LO 0x1040020
127 #define NPS_PKT_MBOX_INT_LO_ENA_W1C 0x1040030
128 #define NPS_PKT_MBOX_INT_LO_ENA_W1S 0x1040038
129 #define NPS_PKT_MBOX_INT_HI 0x1040040
130 #define NPS_PKT_MBOX_INT_HI_ENA_W1C 0x1040050
131 #define NPS_PKT_MBOX_INT_HI_ENA_W1S 0x1040058
132 #define NPS_PKT_IN_RERR_HI 0x1040108
133 #define NPS_PKT_IN_RERR_HI_ENA_W1S 0x1040120
134 #define NPS_PKT_IN_RERR_LO 0x1040128
135 #define NPS_PKT_IN_RERR_LO_ENA_W1S 0x1040140
136 #define NPS_PKT_IN_ERR_TYPE 0x1040148
137 #define NPS_PKT_IN_ERR_TYPE_ENA_W1S 0x1040160
138 #define NPS_PKT_IN_INSTR_CTLX(_i) (0x10060 + ((_i) * 0x40000))
139 #define NPS_PKT_IN_INSTR_BADDRX(_i) (0x10068 + ((_i) * 0x40000))
140 #define NPS_PKT_IN_INSTR_RSIZEX(_i) (0x10070 + ((_i) * 0x40000))
141 #define NPS_PKT_IN_DONE_CNTSX(_i) (0x10080 + ((_i) * 0x40000))
142 #define NPS_PKT_IN_INSTR_BAOFF_DBELLX(_i) (0x10078 + ((_i) * 0x40000))
143 #define NPS_PKT_IN_INT_LEVELSX(_i) (0x10088 + ((_i) * 0x40000))
145 #define NPS_PKT_SLC_RERR_HI 0x1040208
146 #define NPS_PKT_SLC_RERR_HI_ENA_W1S 0x1040220
147 #define NPS_PKT_SLC_RERR_LO 0x1040228
148 #define NPS_PKT_SLC_RERR_LO_ENA_W1S 0x1040240
149 #define NPS_PKT_SLC_ERR_TYPE 0x1040248
150 #define NPS_PKT_SLC_ERR_TYPE_ENA_W1S 0x1040260
152 #define NPS_PKT_MBOX_PF_VF_PFDATAX(_i) (0x1040800 + ((_i) * 0x8))
153 #define NPS_PKT_MBOX_VF_PF_PFDATAX(_i) (0x1040C00 + ((_i) * 0x8))
155 #define NPS_PKT_SLC_CTLX(_i) (0x10000 + ((_i) * 0x40000))
156 #define NPS_PKT_SLC_CNTSX(_i) (0x10008 + ((_i) * 0x40000))
157 #define NPS_PKT_SLC_INT_LEVELSX(_i) (0x10010 + ((_i) * 0x40000))
160 #define POM_INT_ENA_W1S 0x11C0018
161 #define POM_GRP_EXECMASKX(_i) (0x11C1100 | ((_i) * 8))
162 #define POM_INT 0x11C0000
163 #define POM_PERF_CTL 0x11CC400
166 #define BMI_INT 0x1140000
167 #define BMI_CTL 0x1140020
168 #define BMI_INT_ENA_W1S 0x1140018
169 #define BMI_NPS_PKT_CNT 0x1140070
172 #define EFL_CORE_INT_ENA_W1SX(_i) (0x1240018 + ((_i) * 0x400))
173 #define EFL_CORE_VF_ERR_INT0X(_i) (0x1240050 + ((_i) * 0x400))
174 #define EFL_CORE_VF_ERR_INT0_ENA_W1SX(_i) (0x1240068 + ((_i) * 0x400))
175 #define EFL_CORE_VF_ERR_INT1X(_i) (0x1240070 + ((_i) * 0x400))
176 #define EFL_CORE_VF_ERR_INT1_ENA_W1SX(_i) (0x1240088 + ((_i) * 0x400))
177 #define EFL_CORE_SE_ERR_INTX(_i) (0x12400A0 + ((_i) * 0x400))
178 #define EFL_RNM_CTL_STATUS 0x1241800
179 #define EFL_CORE_INTX(_i) (0x1240000 + ((_i) * 0x400))
182 #define BMO_CTL2 0x1180028
183 #define BMO_NPS_SLC_PKT_CNT 0x1180078
186 #define LBC_INT 0x1200000
187 #define LBC_INVAL_CTL 0x1201010
188 #define LBC_PLM_VF1_64_INT 0x1202008
189 #define LBC_INVAL_STATUS 0x1202010
190 #define LBC_INT_ENA_W1S 0x1203000
191 #define LBC_PLM_VF1_64_INT_ENA_W1S 0x1205008
192 #define LBC_PLM_VF65_128_INT 0x1206008
193 #define LBC_ELM_VF1_64_INT 0x1208000
194 #define LBC_PLM_VF65_128_INT_ENA_W1S 0x1209008
195 #define LBC_ELM_VF1_64_INT_ENA_W1S 0x120B000
196 #define LBC_ELM_VF65_128_INT 0x120C000
197 #define LBC_ELM_VF65_128_INT_ENA_W1S 0x120F000
199 #define RST_BOOT 0x10C1600
200 #define FUS_DAT1 0x10C1408
203 #define PEM0_INT 0x1080428
227 * @exec_0_to_39: AE engines 0 to 39 status
338 * @queue_status: 1 = AQMQ is enabled, 0 = AQMQ is disabled
355 * @queue_active: 1 = AQMQ is active, 0 = AQMQ is quiescent
372 * @ae_fuse: Fuse settings for AE 19..0
373 * @se_fuse: Fuse settings for SE 15..0
434 * @ae_wd: Reads or sets enable for EMU(0..3)_WD_INT[AE_WD]
435 * @se_wd: Reads or sets enable for EMU(0..3)_WD_INT[SE_WD]
456 * @ae_ge: Reads or sets enable for EMU(0..3)_GE_INT[AE_GE]
457 * @se_ge: Reads or sets enable for EMU(0..3)_GE_INT[SE_GE]
479 * 1 = Include, 0 = Remove
480 * @z: If set, 8 trailing 0x00 bytes will be added to the end of the
515 * [INT] when [CNT] goes to 0.
671 * @is64b: If 1, the ring uses 64-byte instructions. If 0, the
776 * 0 = allocate per queue
779 * 0 = allocate per queue
782 * 0 = allocate per queue
785 * 0 = allocate per queue
788 * 0 = allocation per queue
821 * @ocla: Set when any OCLA(0)_INT and corresponding OCLA(0_INT_ENA_W1C
836 * @pem: Set when any PEM(0)_INT RO bit is set or when any non-RO
837 * PEM(0)_INT and corresponding PEM(0)_INT_ENA_W1C bit are both set
899 * See EFL_CORE(0..3)_AE_ERR_INT
901 * See EFL_CORE(0..3)_SE_ERR_INT
938 * EFL_CORE(0..3)_INT[EPCI_DECODE_ERR].
940 * EFL_CORE(0..3)_INT[D_LEFT].
942 * EFL_CORE(0..3)_INT[LEN_OVR].
1344 * 0x1 = 1.8V
1345 * 0x2 = 2.5V
1346 * 0x4 = 3.3V
1350 * @rboot: determines whether core 0 remains in reset after