56 #define SYST_CON_REG(to)        (timer_of_base(to) + SYST_CON)
57 #define SYST_VAL_REG(to)        (timer_of_base(to) + SYST_VAL)
139 	val = readl(timer_of_base(to) + GPT_CTRL_REG(timer));  in mtk_gpt_clkevt_time_stop()
140 	writel(val & ~GPT_CTRL_ENABLE, timer_of_base(to) +  in mtk_gpt_clkevt_time_stop()
147 	writel(delay, timer_of_base(to) + GPT_CMP_REG(timer));  in mtk_gpt_clkevt_time_setup()
156 	writel(GPT_IRQ_ACK(timer), timer_of_base(to) + GPT_IRQ_ACK_REG);  in mtk_gpt_clkevt_time_start()
158 	val = readl(timer_of_base(to) + GPT_CTRL_REG(timer));  in mtk_gpt_clkevt_time_start()
169 	       timer_of_base(to) + GPT_CTRL_REG(timer));  in mtk_gpt_clkevt_time_start()
208 	writel(GPT_IRQ_ACK(TIMER_CLK_EVT), timer_of_base(to) + GPT_IRQ_ACK_REG);  in mtk_gpt_interrupt()
218 	       timer_of_base(to) + GPT_CTRL_REG(timer));  in mtk_gpt_setup()
221 	       timer_of_base(to) + GPT_CLK_REG(timer));  in mtk_gpt_setup()
223 	writel(0x0, timer_of_base(to) + GPT_CMP_REG(timer));  in mtk_gpt_setup()
226 	       timer_of_base(to) + GPT_CTRL_REG(timer));  in mtk_gpt_setup()
234 	writel(0x0, timer_of_base(to) + GPT_IRQ_EN_REG);  in mtk_gpt_enable_irq()
237 	writel(0x3f, timer_of_base(to) + GPT_IRQ_ACK_REG);  in mtk_gpt_enable_irq()
239 	val = readl(timer_of_base(to) + GPT_IRQ_EN_REG);  in mtk_gpt_enable_irq()
241 	       timer_of_base(to) + GPT_IRQ_EN_REG);  in mtk_gpt_enable_irq()
297 	clocksource_mmio_init(timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC),  in mtk_gpt_init()
300 	gpt_sched_reg = timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC);  in mtk_gpt_init()