53 static void __iomem *sirfsoc_timer_base;  variable
58 	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) & ~0x7,  in sirfsoc_timer_count_disable()
59 		sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);  in sirfsoc_timer_count_disable()
65 	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x3,  in sirfsoc_timer_count_enable()
66 		sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);  in sirfsoc_timer_count_enable()
76 	writel_relaxed(BIT(cpu), sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);  in sirfsoc_timer_interrupt()
91 	writel_relaxed((readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |  in sirfsoc_timer_read()
92 			BIT(0)) & ~BIT(1), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);  in sirfsoc_timer_read()
94 	cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_HI);  in sirfsoc_timer_read()
95 	cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_LO);  in sirfsoc_timer_read()
108 	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0 +  in sirfsoc_timer_set_next_event()
110 	writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0 +  in sirfsoc_timer_set_next_event()
131 		sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);  in sirfsoc_clocksource_suspend()
139 		writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);  in sirfsoc_clocksource_resume()
142 		sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);  in sirfsoc_clocksource_resume()
144 		sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);  in sirfsoc_clocksource_resume()
146 	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |  in sirfsoc_clocksource_resume()
147 		BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);  in sirfsoc_clocksource_resume()
239 	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);  in sirfsoc_atlas7_timer_init()
240 	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL);  in sirfsoc_atlas7_timer_init()
241 	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_1_CTRL);  in sirfsoc_atlas7_timer_init()
244 	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);  in sirfsoc_atlas7_timer_init()
245 	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);  in sirfsoc_atlas7_timer_init()
246 	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |  in sirfsoc_atlas7_timer_init()
247 		BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);  in sirfsoc_atlas7_timer_init()
248 	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0);  in sirfsoc_atlas7_timer_init()
249 	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_1);  in sirfsoc_atlas7_timer_init()
252 	writel_relaxed(0xFFFF, sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);  in sirfsoc_atlas7_timer_init()
261 	sirfsoc_timer_base = of_iomap(np, 0);  in sirfsoc_of_timer_init()
262 	if (!sirfsoc_timer_base) {  in sirfsoc_of_timer_init()