Lines Matching +full:erratum +full:- +full:unknown1
1 # SPDX-License-Identifier: GPL-2.0-only
163 Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,
186 32-bit free running decrementing counters.
240 bool "Integrator-AP timer driver" if COMPILE_TEST
243 Enables support for the Integrator-AP timer.
276 available on many OMAP-like platforms.
285 It has a 64-bit counter with update rate up to 1000MHz.
286 This counter is accessed via couple of 32-bit memory-mapped registers.
305 bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST
309 These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores
314 bool "Support for 64-bit counters in ARC HS38 cores" if COMPILE_TEST
318 This enables 2 different 64-bit timers: RTC (for UP) and GFRC (for SMP).
336 power-of-2 divisor of the clock rate. The behaviour can also be
339 The main use of the event stream is wfe-based timeouts of userspace
350 bool "Workaround for Freescale/NXP Erratum A-008585"
355 This option enables a workaround for Freescale/NXP Erratum
356 A-008585 ("ARM generic timer may contain an erroneous
358 fsl,erratum-a008585 property is found in the timer node.
361 bool "Workaround for Hisilicon Erratum 161010101"
366 This option enables a workaround for Hisilicon Erratum
367 161010101. The workaround will be active if the hisilicon,erratum-161010101
371 bool "Workaround for Cortex-A73 erratum 858921"
376 This option enables a workaround applicable to Cortex-A73
382 bool "Workaround for Allwinner A64 erratum UNKNOWN1"
389 allwinner,erratum-unknown1 property is found in the timer node.
505 bool "J-Core PIT timer driver" if COMPILE_TEST
511 the integrated PIT in the J-Core synthesizable, open source SoC.
519 the Compare Match Timer (CMT) hardware available in 16/32/48-bit
527 This enables build of a clockevent driver for the Multi-Function
529 This hardware comes with 16-bit timer registers.
544 the 32-bit Timer Unit (TMU) hardware available on a wide range
553 the 48-bit System Timer (STI) hardware available on a SoCs
589 bool "Clocksource for PXA or SA-11x0 platform" if COMPILE_TEST
593 This enables OST0 support available on PXA and SA-11x0
656 bool "Timer for the RISC-V platform" if COMPILE_TEST
661 This enables the per-hart timer built into all RISC-V systems, which
663 required for all RISC-V systems.
666 bool "CLINT Timer for the RISC-V platform" if COMPILE_TEST
671 This option enables the CLINT timer for RISC-V systems. The CLINT
672 driver is usually used for NoMMU RISC-V systems.
675 bool "SMP Timer for the C-SKY platform" if COMPILE_TEST
679 Say yes here to enable C-SKY SMP timer driver used for C-SKY SMP