3  * Zynq UltraScale+ MPSoC Divider support
7  * Adjustable divider clock implementation
16  * DOC: basic adjustable divider clock that cannot gate
32  * struct zynqmp_clk_divider - adjustable divider clock
35  * @is_frac:	The divider is a fractional divider
72  * zynqmp_clk_divider_recalc_rate() - Recalc rate of divider clock
81 	struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw);  in zynqmp_clk_divider_recalc_rate()  local
83 	u32 clk_id = divider->clk_id;  in zynqmp_clk_divider_recalc_rate()
84 	u32 div_type = divider->div_type;  in zynqmp_clk_divider_recalc_rate()
91 		pr_warn_once("%s() get divider failed for %s, ret = %d\n",  in zynqmp_clk_divider_recalc_rate()
99 	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)  in zynqmp_clk_divider_recalc_rate()
103 		WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),  in zynqmp_clk_divider_recalc_rate()
114 				    struct zynqmp_clk_divider *divider,  in zynqmp_get_divider2_val()  argument
136 		for (div2 = 1; div2 <= divider->max_div;) {  in zynqmp_get_divider2_val()
143 			if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)  in zynqmp_get_divider2_val()
156  * zynqmp_clk_divider_round_rate() - Round rate of divider clock
167 	struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw);  in zynqmp_clk_divider_round_rate()  local
169 	u32 clk_id = divider->clk_id;  in zynqmp_clk_divider_round_rate()
170 	u32 div_type = divider->div_type;  in zynqmp_clk_divider_round_rate()
175 	if (divider->flags & CLK_DIVIDER_READ_ONLY) {  in zynqmp_clk_divider_round_rate()
179 			pr_warn_once("%s() get divider failed for %s, ret = %d\n",  in zynqmp_clk_divider_round_rate()
186 		if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)  in zynqmp_clk_divider_round_rate()
192 	bestdiv = zynqmp_divider_get_val(*prate, rate, divider->flags);  in zynqmp_clk_divider_round_rate()
195 	 * In case of two divisors, compute best divider values and return  in zynqmp_clk_divider_round_rate()
197 	 * set to optimum based on required total divider value.  in zynqmp_clk_divider_round_rate()
201 		zynqmp_get_divider2_val(hw, rate, divider, &bestdiv);  in zynqmp_clk_divider_round_rate()
204 	if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && divider->is_frac)  in zynqmp_clk_divider_round_rate()
207 	bestdiv = min_t(u32, bestdiv, divider->max_div);  in zynqmp_clk_divider_round_rate()
214  * zynqmp_clk_divider_set_rate() - Set rate of divider clock
224 	struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw);  in zynqmp_clk_divider_set_rate()  local
226 	u32 clk_id = divider->clk_id;  in zynqmp_clk_divider_set_rate()
227 	u32 div_type = divider->div_type;  in zynqmp_clk_divider_set_rate()
231 	value = zynqmp_divider_get_val(parent_rate, rate, divider->flags);  in zynqmp_clk_divider_set_rate()
240 	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)  in zynqmp_clk_divider_set_rate()
246 		pr_warn_once("%s() set divider failed for %s, ret = %d\n",  in zynqmp_clk_divider_set_rate()
261  * @type:		Divider type
287  * zynqmp_clk_register_divider() - Register a divider clock
294  * Return: clock hardware to registered clock divider
307 	/* allocate the divider */  in zynqmp_clk_register_divider()
328 	 * To achieve best possible rate, maximum limit of divider is required  in zynqmp_clk_register_divider()