73 	 * bits of the v PLL divider. Bit 8 is tied low and always zero,  in vco_get()
80 		vco->v = val & INTEGRATOR_AP_CM_BITS;  in vco_get()
88 	 * access the low eight bits of the v PLL divider. Bit 8 is tied low  in vco_get()
95 		vco->v = val & INTEGRATOR_AP_SYS_BITS;  in vco_get()
105 	 * bit to 0 yields v = 17, r = 22 and OD = 1, whereas setting the  in vco_get()
106 	 * bit to 1 yields v = 14, r = 14 and OD = 1 giving the frequencies  in vco_get()
107 	 * 33 or 25 MHz respectively.  in vco_get()
112 		vco->v = divxy ? 17 : 14;  in vco_get()
120 	 * of the v PLL divider. Bit 8 is tied low and always zero,  in vco_get()
127 		vco->v = val & 0xFF;  in vco_get()
134 		vco->v = (val >> 12) & 0xFF;  in vco_get()
140 	vco->v = val & 0x1ff;  in vco_get()
161 		val = vco.v & 0xFF;  in vco_set()
162 		if (vco.v & 0x100)  in vco_set()
171 		val = vco.v & 0xFF;  in vco_set()
172 		if (vco.v & 0x100)  in vco_set()
181 		val = (vco.v & 0xFF) | vco.s << 8;  in vco_set()
182 		if (vco.v & 0x100)  in vco_set()
189 		val = ((vco.v & 0xFF) << 12) | (vco.s << 20);  in vco_set()
190 		if (vco.v & 0x100)  in vco_set()
198 		val = vco.v | (vco.r << 9) | (vco.s << 16);  in vco_set()
273 		 * If we're below or less than halfway from 25 to 33 MHz  in icst_round_rate()
274 		 * select 25 MHz  in icst_round_rate()
470 	/* Minimum 25 MHz */
471 	.vd_min		= 25,