Lines Matching +full:6 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012 ST-Ericsson SA
11 #include <linux/clk-provider.h>
12 #include <linux/mfd/dbx500-prcmu.h>
15 #define PRCC_NUM_PERIPH_CLUSTERS 6
22 #define PRCC_SHOW(clk, base, bit) \ argument
23 clk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit]
24 #define PRCC_PCLK_STORE(clk, base, bit) \ argument
25 prcc_pclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
26 #define PRCC_KCLK_STORE(clk, base, bit) \ argument
27 prcc_kclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
33 unsigned int base, bit; in ux500_twocell_get() local
35 if (clkspec->args_count != 2) in ux500_twocell_get()
36 return ERR_PTR(-EINVAL); in ux500_twocell_get()
38 base = clkspec->args[0]; in ux500_twocell_get()
39 bit = clkspec->args[1]; in ux500_twocell_get()
41 if (base != 1 && base != 2 && base != 3 && base != 5 && base != 6) { in ux500_twocell_get()
43 return ERR_PTR(-EINVAL); in ux500_twocell_get()
46 return PRCC_SHOW(clk_data, base, bit); in ux500_twocell_get()
100 switch (fw_version->project) { in u8500_clk_init()
254 /* PRCC P-clocks */ in u8500_clk_init()
256 BIT(0), 0); in u8500_clk_init()
260 BIT(1), 0); in u8500_clk_init()
264 BIT(2), 0); in u8500_clk_init()
268 BIT(3), 0); in u8500_clk_init()
272 BIT(4), 0); in u8500_clk_init()
276 BIT(5), 0); in u8500_clk_init()
280 BIT(6), 0); in u8500_clk_init()
281 PRCC_PCLK_STORE(clk, 1, 6); in u8500_clk_init()
284 BIT(7), 0); in u8500_clk_init()
288 BIT(8), 0); in u8500_clk_init()
292 BIT(9), 0); in u8500_clk_init()
296 BIT(10), 0); in u8500_clk_init()
300 BIT(11), 0); in u8500_clk_init()
304 BIT(0), 0); in u8500_clk_init()
308 BIT(1), 0); in u8500_clk_init()
312 BIT(2), 0); in u8500_clk_init()
316 BIT(3), 0); in u8500_clk_init()
320 BIT(4), 0); in u8500_clk_init()
324 BIT(5), 0); in u8500_clk_init()
328 BIT(6), 0); in u8500_clk_init()
329 PRCC_PCLK_STORE(clk, 2, 6); in u8500_clk_init()
332 BIT(7), 0); in u8500_clk_init()
336 BIT(8), 0); in u8500_clk_init()
340 BIT(9), 0); in u8500_clk_init()
344 BIT(10), 0); in u8500_clk_init()
348 BIT(11), 0); in u8500_clk_init()
352 BIT(12), 0); in u8500_clk_init()
356 BIT(0), 0); in u8500_clk_init()
360 BIT(1), 0); in u8500_clk_init()
364 BIT(2), 0); in u8500_clk_init()
368 BIT(3), 0); in u8500_clk_init()
372 BIT(4), 0); in u8500_clk_init()
376 BIT(5), 0); in u8500_clk_init()
380 BIT(6), 0); in u8500_clk_init()
381 PRCC_PCLK_STORE(clk, 3, 6); in u8500_clk_init()
384 BIT(7), 0); in u8500_clk_init()
388 BIT(8), 0); in u8500_clk_init()
392 BIT(0), 0); in u8500_clk_init()
396 BIT(1), 0); in u8500_clk_init()
400 BIT(0), 0); in u8500_clk_init()
401 PRCC_PCLK_STORE(clk, 6, 0); in u8500_clk_init()
404 BIT(1), 0); in u8500_clk_init()
405 PRCC_PCLK_STORE(clk, 6, 1); in u8500_clk_init()
408 BIT(2), 0); in u8500_clk_init()
409 PRCC_PCLK_STORE(clk, 6, 2); in u8500_clk_init()
412 BIT(3), 0); in u8500_clk_init()
413 PRCC_PCLK_STORE(clk, 6, 3); in u8500_clk_init()
416 BIT(4), 0); in u8500_clk_init()
417 PRCC_PCLK_STORE(clk, 6, 4); in u8500_clk_init()
420 BIT(5), 0); in u8500_clk_init()
421 PRCC_PCLK_STORE(clk, 6, 5); in u8500_clk_init()
424 BIT(6), 0); in u8500_clk_init()
425 PRCC_PCLK_STORE(clk, 6, 6); in u8500_clk_init()
428 BIT(7), 0); in u8500_clk_init()
429 PRCC_PCLK_STORE(clk, 6, 7); in u8500_clk_init()
431 /* PRCC K-clocks in u8500_clk_init()
434 * by enabling just the K-clock, even if it is not a valid parent to in u8500_clk_init()
435 * the K-clock. Until drivers get fixed we might need some kind of in u8500_clk_init()
441 bases[CLKRST1_INDEX], BIT(0), CLK_SET_RATE_GATE); in u8500_clk_init()
445 bases[CLKRST1_INDEX], BIT(1), CLK_SET_RATE_GATE); in u8500_clk_init()
449 bases[CLKRST1_INDEX], BIT(2), CLK_SET_RATE_GATE); in u8500_clk_init()
453 bases[CLKRST1_INDEX], BIT(3), CLK_SET_RATE_GATE); in u8500_clk_init()
457 bases[CLKRST1_INDEX], BIT(4), CLK_SET_RATE_GATE); in u8500_clk_init()
461 bases[CLKRST1_INDEX], BIT(5), CLK_SET_RATE_GATE); in u8500_clk_init()
465 bases[CLKRST1_INDEX], BIT(6), CLK_SET_RATE_GATE); in u8500_clk_init()
466 PRCC_KCLK_STORE(clk, 1, 6); in u8500_clk_init()
469 bases[CLKRST1_INDEX], BIT(8), CLK_SET_RATE_GATE); in u8500_clk_init()
473 bases[CLKRST1_INDEX], BIT(9), CLK_SET_RATE_GATE); in u8500_clk_init()
477 bases[CLKRST1_INDEX], BIT(10), CLK_SET_RATE_GATE); in u8500_clk_init()
482 bases[CLKRST2_INDEX], BIT(0), CLK_SET_RATE_GATE); in u8500_clk_init()
486 bases[CLKRST2_INDEX], BIT(2), CLK_SET_RATE_GATE); in u8500_clk_init()
490 bases[CLKRST2_INDEX], BIT(3), CLK_SET_RATE_GATE); in u8500_clk_init()
494 bases[CLKRST2_INDEX], BIT(4), CLK_SET_RATE_GATE); in u8500_clk_init()
498 bases[CLKRST2_INDEX], BIT(5), CLK_SET_RATE_GATE); in u8500_clk_init()
503 bases[CLKRST2_INDEX], BIT(6), in u8500_clk_init()
505 PRCC_KCLK_STORE(clk, 2, 6); in u8500_clk_init()
508 bases[CLKRST2_INDEX], BIT(7), in u8500_clk_init()
514 bases[CLKRST3_INDEX], BIT(1), CLK_SET_RATE_GATE); in u8500_clk_init()
518 bases[CLKRST3_INDEX], BIT(2), CLK_SET_RATE_GATE); in u8500_clk_init()
522 bases[CLKRST3_INDEX], BIT(3), CLK_SET_RATE_GATE); in u8500_clk_init()
526 bases[CLKRST3_INDEX], BIT(4), CLK_SET_RATE_GATE); in u8500_clk_init()
530 bases[CLKRST3_INDEX], BIT(5), CLK_SET_RATE_GATE); in u8500_clk_init()
534 bases[CLKRST3_INDEX], BIT(6), CLK_SET_RATE_GATE); in u8500_clk_init()
535 PRCC_KCLK_STORE(clk, 3, 6); in u8500_clk_init()
538 bases[CLKRST3_INDEX], BIT(7), CLK_SET_RATE_GATE); in u8500_clk_init()
543 bases[CLKRST6_INDEX], BIT(0), CLK_SET_RATE_GATE); in u8500_clk_init()
544 PRCC_KCLK_STORE(clk, 6, 0); in u8500_clk_init()
549 if (of_node_name_eq(child, "prcmu-clock")) { in u8500_clk_init()
554 if (of_node_name_eq(child, "prcc-periph-clock")) in u8500_clk_init()
557 if (of_node_name_eq(child, "prcc-kernel-clock")) in u8500_clk_init()
560 if (of_node_name_eq(child, "rtc32k-clock")) in u8500_clk_init()
563 if (of_node_name_eq(child, "smp-twd-clock")) in u8500_clk_init()
567 CLK_OF_DECLARE(u8500_clks, "stericsson,u8500-clks", u8500_clk_init);